Guided courses

Self-paced courses you work through chapter by chapter, with labs that only count when the pass check is met and projects reviewed by an engineer. This is the other way to learn here: the same depth as the live cohorts, at your own pace, without waiting for a date.

36guided courses

12learning paths

137graded labs

22reviewed projects

Learning paths

Start here. A path is an ordered set of courses with one goal, a capstone you build, and a badge that means something because the work behind it was assessed. Courses can also be taken on their own.

Network Systems Architect

design a network stack end to end, from the kernel to the NIC to the cluster, and defend the choices.

PDP-01 → DPK-01 → RDM-01 → RDM-02 → OFL-04 → CNT-01 → SEC-01 → OBS-03

≈ 230 hBadge: Systems ArchitectFlagship

Cloud-Native Network Engineer

design, secure, and operate the network of a Kubernetes platform.

PDP-01 → PDP-03 → CNT-01 → OBS-02 → CNT-02 → PDP-02

≈ 160 hBadge: Cluster Network Engineer

Digital Design with Verilog

write Verilog that simulates correctly and synthesizes as intended.

VLG-01 → VLG-02 → VLG-03 → VLG-08 → VLG-04 → VLG-09 → VLG-06 → VLG-07 → VLG-05

≈ 84 hBadge: RTL Designer

HPC Interconnect Engineer

run MPI and GPU workloads across an RDMA fabric and keep them fast.

RDM-01 → RDM-02 → RDM-03 → RDM-04 → RDM-05 → OFL-04

≈ 180 hBadge: RDMA Fabric Engineer

Hardware Acceleration Engineer

decide what runs on the NIC, the DPU, or the FPGA, and build it.

VLG-01 → VLG-03 → VLG-04 → OFL-01 → OFL-02 → OFL-03 → OFL-04 → VLG-05

≈ 220 h (includes the Verilog path)Badge: Offload Engineer

Network Foundations

understand how packets really move in Linux before tuning anything.

PDP-01 → PDP-02 → DPK-01 → OBS-02

≈ 110 hBadge: Packet Path Analyst

Network Performance Engineer

measure, explain, and improve throughput, latency, and congestion.

PDP-01 → TRN-01 → OBS-03 → OBS-02 → RDM-02

≈ 150 hBadge: Performance Analyst

Packet Processing Developer

build fast packet software in user space.

PDP-01 → DPK-01 → DPK-02 → DPK-03 → OFL-01

≈ 150 hBadge: DPDK Developer

Programmable Network and Automation

change network behaviour in software and test it automatically.

PDP-04 → PDP-02 → OBS-03 → OBS-01

≈ 150 hBadge: Programmable Network Engineer

Telco and 5G Data Plane

build the user plane of a mobile core and run it on cloud infrastructure.

CNT-03 → DPK-03 → DPK-01 → TRN-02 → CNT-01

≈ 190 hBadge: User-Plane Engineer

Verilog to Networking Hardware

connect RTL skills to packet hardware (CRC, FIFOs, FPGA NICs).

VLG-01 → VLG-03 → VLG-06 → OFL-01 → DPK-01

≈ 110 hBadge: Hardware Packet Engineer

Zero-Trust Security Engineer

enforce zero-trust policy at line rate and prove it works.

SEC-01 → SEC-02 → OFL-02 → PDP-02 → OBS-01

≈ 170 hBadge: Zero-Trust Architect

Domains

PDPProgrammable Data PlanesRewrite what the network does, one packet at a time.4 courses DPKPacket Processing with DPDKTake the kernel out of the packet path and keep the packets.3 courses RDMRDMA and HPC InterconnectMove data between machines without waiting for the CPU.5 courses OFLHardware Offload and VirtualizationDecide what the card should do, and prove it was the right call.4 courses CNTCloud-Native and Telco InfrastructureBuild the networks that carry clusters and phones.3 courses SECSecurity and Zero TrustTrust nothing, check everything, and keep it fast.2 courses OBSObservability, Testing and AutomationKnow what the network is doing before the user tells you.3 courses TRNTransport and EdgeGet the bytes there on time, every time.2 courses VLGDigital Design with VerilogWrite the hardware, then prove it works before it exists.9 courses

Every guided course

PDP-01≈ 30 h Inside the Linux Kernel Network Stack Follow a single packet from the NIC driver to a socket and back, and say what happens at each step. IntermediateProgrammable Data Planes 5 units3 labs PDP-02≈ 30 h eBPF and XDP: Programmable Kernel Networking Write, verify, load, and debug eBPF programs, and build an XDP data plane that drops, redirects, and measures traffic. AdvancedProgrammable Data Planes 6 units4 labs PDP-03≈ 30 h Container Networking, CNI and Cilium Build a CNI plugin by hand, then run a cluster network with eBPF-based policy, load balancing, and observability. IntermediateProgrammable Data Planes 6 units4 labs PDP-04≈ 30 h Network Programmability with P4 Write a P4 pipeline, control it through P4Runtime, and build a firewall and a load balancer on a programmable switch model. IntermediateProgrammable Data Planes 6 units4 labs DPK-01≈ 30 h DPDK in Depth Build high-speed packet applications on DPDK's core libraries and finish with a VPN gateway. AdvancedPacket Processing with DPDKIn final review 8 units4 labs DPK-02≈ 30 h Build a User-Space TCP/IP Stack on DPDK Write a working user-space TCP/IP stack and put an HTTP proxy on top of it. AdvancedPacket Processing with DPDK 6 units4 labs DPK-03≈ 30 h NFV and DPDK Performance Design network functions as virtual services and make them fast with DPDK, SR-IOV, and SFC. AdvancedPacket Processing with DPDK 7 units4 labs RDM-01≈ 30 h RDMA Programming with Verbs Write verbs programs for two-sided, one-sided, and atomic operations, and tune them. IntermediateRDMA and HPC InterconnectIn final review 9 units5 labs RDM-02≈ 30 h RoCEv2 and Converged Fabric Deployment Design, configure, and troubleshoot a lossless Ethernet fabric that carries RDMA alongside TCP/IP. IntermediateRDMA and HPC InterconnectIn final review 7 units5 labs RDM-03≈ 30 h RDMA and MPI in High-Performance Computing Explain how MPI reaches the wire through OFI and UCX, and tune a real MPI job. AdvancedRDMA and HPC Interconnect 9 units4 labs RDM-04≈ 30 h RDMA for Distributed Storage (Ceph) Find where a storage cluster loses time to TCP, enable RDMA in Ceph, and prove the gain with measurements. AdvancedRDMA and HPC InterconnectIn final review 7 units4 labs RDM-05≈ 30 h GPUDirect and SR-IOV for HPC Move GPU data across the cluster without a CPU copy, and keep the path fast in a multi-tenant system. AdvancedRDMA and HPC Interconnect 9 units4 labs OFL-01≈ 30 h SmartNIC and DPU Acceleration Decide what belongs on the card, program a SmartNIC or DPU, and deploy accelerated workloads on Kubernetes. AdvancedHardware Offload and Virtualization 8 units4 labs OFL-02≈ 30 h Crypto NIC and TLS Offload Offload TLS to hardware, configure real servers to use it, and prove the throughput and CPU gains. AdvancedHardware Offload and Virtualization 9 units4 labs OFL-03≈ 30 h PCIe Passthrough and Virtual Network Performance Choose between passthrough, SR-IOV, virtio, and accelerated vSwitches for a workload, and measure the difference. AdvancedHardware Offload and Virtualization 10 units4 labs OFL-04≈ 30 h SR-IOV: Principles and Practice Build an SR-IOV lab from scratch and run it in a VM, a container, and a cloud platform. IntermediateHardware Offload and Virtualization 8 units4 labs CNT-01≈ 30 h Advanced Kubernetes Networking and Service Mesh Design a service mesh, a multi-cluster network, and a GitOps workflow that holds up in production. AdvancedCloud-Native and Telco Infrastructure 8 units4 labs CNT-02≈ 30 h Network Design for Hyperconverged Infrastructure Design the network for a hyperconverged rack: topology, storage traffic, automation, and high availability. IntermediateCloud-Native and Telco InfrastructureIn final review 8 units4 labs CNT-03≈ 30 h 5G Core UPF Data-Plane Development Build the forwarding and charging logic of a 5G user-plane function and run it on DPDK or VPP. AdvancedCloud-Native and Telco InfrastructureSome chapters are still being completed 9 units4 labs SEC-01≈ 29 h Zero-Trust Networking and the High-Performance Security Gateway Design a zero-trust access path and a high-performance gateway, from policy engine to compliance evidence. AdvancedSecurity and Zero TrustSome chapters are still being completed 9 units4 labs SEC-02≈ 30 h Firewall-as-a-Service on DPDK Build a stateful firewall service on DPDK, with ACLs, NAT, session tables, and a control plane. AdvancedSecurity and Zero Trust 8 units4 labs OBS-01≈ 30 h Telemetry and AIOps for Networks Build a streaming telemetry pipeline, detect anomalies, and find root causes with a model you can explain. AdvancedObservability, Testing and Automation 6 units4 labs OBS-02≈ 30 h Cloud-Native Network Performance and Monitoring Find the bottleneck in a cluster network, measure it, and set an SLA you can keep. IntermediateObservability, Testing and Automation 7 units4 labs OBS-03≈ 30 h Automated Network Testing with TRex and Kitune Script repeatable traffic tests, collect and analyze the results, and publish a benchmark report. IntermediateObservability, Testing and Automation 7 units4 labs TRN-01≈ 30 h TCP BBR and Custom Congestion Control Understand BBR's model, read its kernel code, and build and evaluate a custom congestion-control module. AdvancedTransport and Edge 8 units4 labs TRN-02≈ 30 h Low-Latency Networking for Edge Computing Design an edge network where every millisecond is budgeted: placement, QoS, time-sensitive transport, and mobility. IntermediateTransport and EdgeSome chapters are still being completed 7 units4 labs VLG-01≈ 12 h Verilog Foundations: Modules, Dataflow, Behaviour Write your first modules in three styles, and know why each one exists. FoundationsDigital Design with Verilog 4 units3 labs VLG-02≈ 10 h Testbenches and Simulation Write self-checking testbenches with clocks, stimulus, monitors, and timing checks. FoundationsDigital Design with Verilog 4 units4 labs VLG-03≈ 14 h Combinational, Sequential and Memory Design Design combinational blocks from truth tables, sequential blocks from state diagrams, and memory from IP or a compiler. IntermediateDigital Design with Verilog 3 units4 labs VLG-04≈ 12 h Synthesis-Ready RTL and Hardware Mapping Read your RTL the way a synthesizer does: know which constructs become wires, latches, flip-flops, or priority logic, and fix the ones that surprise you. IntermediateDigital Design with Verilog 6 units4 labs VLG-05≈ 6 h FPGA Primitives (Xilinx) Instantiate the device's own primitives where the synthesizer's inference is not enough. AdvancedDigital Design with VerilogIn final review 4 units3 labs VLG-06≈ 10 h The Verilog Circuit Cookbook Build the blocks that appear in almost every real design: CRC, pseudo-random generators, dual-port RAM, and FIFOs including the clock-domain-crossing version. IntermediateDigital Design with VerilogIn final review 4 units4 labs VLG-07≈ 20 h Verilog by Example: The 140-Example Lab Bank Practise with about 140 short designs, each with a testbench, grouped by topic so you can drill one skill at a time. FoundationsDigital Design with Verilog 0 units4 labs VLG-08≈ 10 h FSM Design with Verilog Design, code, and verify Moore and Mealy controllers and sequence detectors, and choose a state encoding for area, power, or speed. IntermediateDigital Design with VerilogIn final review 6 units2 labs VLG-09≈ 16 h RTL Design with Verilog Write RTL that simulates and synthesizes as intended, then measure its timing and area. IntermediateDigital Design with VerilogIn final review 11 units2 labs

Labs and projects

Every course carries four labs, and each lab has a chapter, an environment, a time budget, something you submit and a pass check that either passes or does not. Lab environments are tagged vm, container, sim or hardware, and anything needing hardware has a simulator fallback so nobody is blocked by equipment.

Beyond the labs there are 13 multi-stage lab sequences built around a scenario — an outage, a design request, a constraint — with faults injected that you have to find, acceptance tests that pass or fail, and a timed graded practical at the end.

Projects run two to four weeks part-time. Each has a brief, milestones, deliverables and a review call with an experienced engineer; the review is the credential, not the certificate. A project passes at 70% across five criteria with no zero on any of them.

See the labs See the projects

Prefer a live cohort?

The instructor-led courses run as scheduled cohorts in three timezone bands, with the same labs delivered live.

Live online dates