VLG-04 · Digital Design with Verilog
Write code the synthesizer reads the way you meant.
Find the latches and mismatches that pass simulation and fail on the board, then rewrite the code so they cannot.
You build: cleaned RTL and a list of each fix with the rule behind it.
Promise
Read your RTL the way a synthesizer does: know which constructs become wires, latches, flip-flops, or priority logic, and fix the ones that surprise you.
Prerequisites
VLG-03.
Units
1. wire versus reg, and sensitivity lists `hdl_design_ch09` sections 9.1, 9.3
.
2. Assignments and operators ch09 sections 9.2, and the hardware-semantics note sections 2–4
.
3. Latches and flip-flops hardware-semantics note sections 5, 8
the inference rules.
4. Priority and loops ch09 sections 9.6–9.7; note section 6–7
.
5. Pipelining and balance ch09 sections 9.4–9.5
.
6. Duplication and sharing ch09 section 9.8; note section 10
.
Labs
Each lab names its environment and a pass check. Labs are not marked complete on "it ran" — the pass check has to hold.
| Lab | What you do | Environment |
|---|---|---|
| VLG-04ach ch 9 | Find unintended latches in a given modulePass check: All latches named with their cause | sim60 min |
| VLG-04bch ch 9 | Pipeline a multiply-addPass check: Latency and throughput stated | sim90 min |
| VLG-04cch ch 9 | Share one adder across two operationsPass check: Area and delay reported | sim90 min |
| VLG-04dch ch 9 | Priority versus parallel casePass check: Structure explained | sim60 min |
Capstone project · CAP-19
Synthesis Cleanup · 1 week
A module failed review for latches and simulation mismatch.
Fix the module, prove it with a testbench, and list the five fixes with their rules.
Deliverables: Fixed RTL, testbench, change list.
Outcomes
- I can find every unintended latch in a module and say which rule creates it.
- I can pipeline a multiply-add and state the latency it adds.
- I can decide between duplicating logic and sharing it, using a timing argument.
Also in
How it runs
Work through the units in order. Each unit groups the chapters of the study guide with its share of the labs. You can start any time; there is no cohort date and nothing expires.
Labs run in a VM, a container, a simulator or on real hardware, and the card above names which. Where a lab needs hardware — an RDMA NIC, a programmable switch model, an FPGA — there is a simulator fallback so you are never blocked by equipment.
Questions
Do I get a certificate?
You get a completion record for the course. Path badges and project credentials are earned by passing the labs and the project review, not by attendance.
Can my team take this together?
Yes — and if you would rather have it delivered live, with the instructor in the room, this course also exists as a scheduled live cohort. See the live dates.
How long does it take?
≈ 12 h of study including the labs. Most engineers take it part-time over a few weeks.