Digital Design with Verilog
Write the hardware, then prove it works before it exists.
9 courses34 labs
digital designers, FPGA engineers, and anyone whose networking work meets the hardware.
What you will be able to do
- Write modules in structural, dataflow, and behavioural styles and know when each fits.
- Write self-checking testbenches with clocks, stimulus, and monitors.
- Design FSMs, counters, FIFOs, and CRC blocks that synthesize cleanly.
- Recognize and fix latch inference, unintended priority, and sensitivity-list errors.
Courses
VLG-01≈ 12 h
Verilog Foundations: Modules, Dataflow, Behaviour
Write your first modules in three styles, and know why each one exists.
4 units3 labs
VLG-02≈ 10 h
Testbenches and Simulation
Write self-checking testbenches with clocks, stimulus, monitors, and timing checks.
4 units4 labs
VLG-03≈ 14 h
Combinational, Sequential and Memory Design
Design combinational blocks from truth tables, sequential blocks from state diagrams, and memory from IP or a compiler.
3 units4 labs
VLG-04≈ 12 h
Synthesis-Ready RTL and Hardware Mapping
Read your RTL the way a synthesizer does: know which constructs become wires, latches, flip-flops, or priority logic, and fix the ones that surprise you.
6 units4 labs
VLG-05≈ 6 h
FPGA Primitives (Xilinx)
Instantiate the device's own primitives where the synthesizer's inference is not enough.
4 units3 labs
VLG-06≈ 10 h
The Verilog Circuit Cookbook
Build the blocks that appear in almost every real design: CRC, pseudo-random generators, dual-port RAM, and FIFOs including the clock-domain-crossing version.
4 units4 labs
VLG-07≈ 20 h
Verilog by Example: The 140-Example Lab Bank
Practise with about 140 short designs, each with a testbench, grouped by topic so you can drill one skill at a time.
0 units4 labs
VLG-08≈ 10 h
FSM Design with Verilog
Design, code, and verify Moore and Mealy controllers and sequence detectors, and choose a state encoding for area, power, or speed.
6 units2 labs
VLG-09≈ 16 h
RTL Design with Verilog
Write RTL that simulates and synthesizes as intended, then measure its timing and area.
11 units2 labs