Verilog to Networking Hardware
connect RTL skills to packet hardware (CRC, FIFOs, FPGA NICs).
≈ 110 hBadge: Hardware Packet Engineer
Who it is for
Verilog graduates who want to work on network cards or FPGA data paths.
The sequence
- 1VLG-01 · Verilog Foundations: Modules, Dataflow, Behaviour Write your first modules in three styles, and know why each one exists.
- 2VLG-03 · Combinational, Sequential and Memory Design Design combinational blocks from truth tables, sequential blocks from state diagrams, and memory from IP or a compiler.
- 3VLG-06 · The Verilog Circuit Cookbook Build the blocks that appear in almost every real design: CRC, pseudo-random generators, dual-port RAM, and FIFOs including the clock-domain-crossing version.
- 4OFL-01 · SmartNIC and DPU Acceleration Decide what belongs on the card, program a SmartNIC or DPU, and deploy accelerated workloads on Kubernetes.
- 5DPK-01 · DPDK in Depth Build high-speed packet applications on DPDK's core libraries and finish with a VPN gateway.
Capstone
CRC-checked packet ingress block in RTL (CAP-12)
Take the first course
Every course in the path can be taken on its own, in any order.