VLG-05 · Digital Design with Verilog
Use the silicon's own building blocks.
Instantiate clock buffers, block RAM and DSP slices directly, and check the results on real hardware.
You build: primitive-based test designs run on an FPGA board.
In final review — the chapters for this course are still being finalised.
Promise
Instantiate the device's own primitives where the synthesizer's inference is not enough.
Prerequisites
VLG-04; access to a Xilinx toolchain for the labs.
Units
1. What a primitive is, and how to instantiate one `xilinx_primitives_usage` sections 1–2
.
2. Calculation and clocking sections 4–5
DSP48, global and regional clock buffers, clock managers.
3. Configuration, serial, I/O sections 6–8
.
4. Memory and processors sections 9–10
distributed RAM, block RAM, FIFOs.
Labs
Each lab names its environment and a pass check. Labs are not marked complete on "it ran" — the pass check has to hold.
| Lab | What you do | Environment |
|---|---|---|
| VLG-05ach primitives | Clock buffer instantiationPass check: Clock reaches the target | hardware60 min |
| VLG-05bch primitives | Block RAM with initial contentsPass check: Read-back correct | hardware90 min |
| VLG-05cch primitives | DSP48 multiply-accumulatePass check: Output matches the model | hardware90 min |
Capstone project · CAP-07
Offload Plan with Measured Gains · 3 weeks
Management asks whether a virtual switch should move to a SmartNIC or DPU.
Baseline the host, measure the offload on the same workload, decide, and state the workload where offload loses.
Deliverables: Measurement data, decision record, rollout plan.
Outcomes
- I can instantiate a block RAM with a chosen width and initial contents.
- I can say which clock buffer to use for a global, a regional, or an I/O clock.
- I can check that a primitive exists on my target family before using it.
Also in
How it runs
Work through the units in order. Each unit groups the chapters of the study guide with its share of the labs. You can start any time; there is no cohort date and nothing expires.
Labs run in a VM, a container, a simulator or on real hardware, and the card above names which. Where a lab needs hardware — an RDMA NIC, a programmable switch model, an FPGA — there is a simulator fallback so you are never blocked by equipment.
Questions
Do I get a certificate?
You get a completion record for the course. Path badges and project credentials are earned by passing the labs and the project review, not by attendance.
Can my team take this together?
Yes — and if you would rather have it delivered live, with the instructor in the room, this course also exists as a scheduled live cohort. See the live dates.
How long does it take?
≈ 6 h of study including the labs. Most engineers take it part-time over a few weeks.