VLG-03 · Digital Design with Verilog
From truth table to state machine to RAM.
Design blocks from truth tables, counters and detectors from state diagrams, and memory you can read back and trust.
You build: a modulo counter, a sequence detector and a RAM read-back test.
Promise
Design combinational blocks from truth tables, sequential blocks from state diagrams, and memory from IP or a compiler.
Prerequisites
VLG-01, VLG-02.
Units
1. Combinational design `hdl_design_ch06`
the design flow from truth table to HDL; multiplexers, demultiplexers, encoders, decoders, comparators, adders.
2. Sequential design `hdl_design_ch07`
analysis method, flip-flops, counters (any modulus, cascaded, shift type), shift registers, sequence generators, FSMs (Mealy and Moore).
3. Memory `hdl_design_ch08`
memory classes, decoding, IP-core RAM on an FPGA, memory-compiler RAM for ASIC, read–write test benches.
Labs
Each lab names its environment and a pass check. Labs are not marked complete on "it ran" — the pass check has to hold.
| Lab | What you do | Environment |
|---|---|---|
| VLG-03ach ch 6 | Voting circuit from truth tablePass check: Matches the specification table | sim90 min |
| VLG-03bch ch 7 | Modulo-N counter with self-startPass check: Recovers from an illegal state | sim90 min |
| VLG-03cch ch 7 | Sequence detector as Mealy and as MoorePass check: Both detect the same sequence | sim90 min |
| VLG-03dch ch 8 | RAM write and read-back testPass check: All addresses match | sim90 min |
Capstone project · CAP-11
Self-Checking FIFO with Clock-Domain Crossing · 2 weeks
A block must pass data between two clocks at unknown ratios.
Implement the FIFO with Gray-coded pointers. Verify with a self-checking testbench across three clock ratios.
Deliverables: RTL, testbench, coverage report, synthesis report.
Outcomes
- I can derive a state machine from a sequence to be detected and implement it as Mealy and as Moore.
- I can design a modulo-N counter and explain its self-start behaviour.
- I can explain when to choose IP-core RAM over a memory compiler.
Also in
How it runs
Work through the units in order. Each unit groups the chapters of the study guide with its share of the labs. You can start any time; there is no cohort date and nothing expires.
Labs run in a VM, a container, a simulator or on real hardware, and the card above names which. Where a lab needs hardware — an RDMA NIC, a programmable switch model, an FPGA — there is a simulator fallback so you are never blocked by equipment.
Questions
Do I get a certificate?
You get a completion record for the course. Path badges and project credentials are earned by passing the labs and the project review, not by attendance.
Can my team take this together?
Yes — and if you would rather have it delivered live, with the instructor in the room, this course also exists as a scheduled live cohort. See the live dates.
How long does it take?
≈ 14 h of study including the labs. Most engineers take it part-time over a few weeks.