VLG-02 · Digital Design with Verilog
Prove the circuit before it exists.
Build testbenches that drive stimulus, check results automatically, and catch the bug before the chip does.
You build: self-checking testbenches with clocks, monitors and timing checks.
Promise
Write self-checking testbenches with clocks, stimulus, monitors, and timing checks.
Prerequisites
VLG-01.
Units
1. Testbench structure `hdl_design_ch05`, sections 5.1–5.2
port-less top, stimulus as `reg`, observed as `wire`, instance, initial and always.
2. Stimulus and time control ch05 sections 5.3–5.5
delays, events, `wait`, tasks and functions, combinational and sequential environments.
3. System tasks ch05 section 5.6 and examples 8.x
`$display`, `$strobe`, `$monitor`, `$finish`, `$time`, `$random`.
4. Delays and timing checks ch05 sections 5.8–5.9; examples 8.x
`specify`, path delays, setup and hold checks.
Labs
Each lab names its environment and a pass check. Labs are not marked complete on "it ran" — the pass check has to hold.
| Lab | What you do | Environment |
|---|---|---|
| VLG-02ach ch 5 | Counter testbench with automatic checksPass check: Pass and fail both reported | sim60 min |
| VLG-02bch ch 5 | Clock with duty cycle and phase shiftPass check: Measured duty cycle correct | sim45 min |
| VLG-02cch ch 5 | `$monitor` and `$strobe` comparisonPass check: Explained in your notes | sim45 min |
| VLG-02dch ch 5 | Timing check on a flip-flopPass check: Violation reported | sim60 min |
Capstone project · CAP-18
8-Bit ALU with Self-Checking Testbench · 1 week
First RTL project for the digital track, reviewed to professional standard.
Implement the ALU with a defined operation set, flags, and a reference-model testbench.
Deliverables: RTL, testbench, synthesis report.
Outcomes
- I can write a testbench that checks results automatically and reports pass or fail.
- I can generate a clock with a chosen duty cycle and a phase shift.
- I can add a setup and hold check and show when it fires.
Also in
How it runs
Work through the units in order. Each unit groups the chapters of the study guide with its share of the labs. You can start any time; there is no cohort date and nothing expires.
Labs run in a VM, a container, a simulator or on real hardware, and the card above names which. Where a lab needs hardware — an RDMA NIC, a programmable switch model, an FPGA — there is a simulator fallback so you are never blocked by equipment.
Questions
Do I get a certificate?
You get a completion record for the course. Path badges and project credentials are earned by passing the labs and the project review, not by attendance.
Can my team take this together?
Yes — and if you would rather have it delivered live, with the instructor in the room, this course also exists as a scheduled live cohort. See the live dates.
How long does it take?
≈ 10 h of study including the labs. Most engineers take it part-time over a few weeks.