Digital Design with Verilog

write Verilog that simulates correctly and synthesizes as intended.

≈ 84 hBadge: RTL Designer

Who it is for

anyone starting in digital hardware, or in FPGA work.

The sequence

  1. 1
    VLG-01 · Verilog Foundations: Modules, Dataflow, Behaviour Write your first modules in three styles, and know why each one exists.
  2. 2
    VLG-02 · Testbenches and Simulation Write self-checking testbenches with clocks, stimulus, monitors, and timing checks.
  3. 3
    VLG-03 · Combinational, Sequential and Memory Design Design combinational blocks from truth tables, sequential blocks from state diagrams, and memory from IP or a compiler.
  4. 4
    VLG-08 · FSM Design with Verilog Design, code, and verify Moore and Mealy controllers and sequence detectors, and choose a state encoding for area, power, or speed.
  5. 5
    VLG-04 · Synthesis-Ready RTL and Hardware Mapping Read your RTL the way a synthesizer does: know which constructs become wires, latches, flip-flops, or priority logic, and fix the ones that surprise you.
  6. 6
    VLG-09 · RTL Design with Verilog Write RTL that simulates and synthesizes as intended, then measure its timing and area.
  7. 7
    VLG-06 · The Verilog Circuit Cookbook Build the blocks that appear in almost every real design: CRC, pseudo-random generators, dual-port RAM, and FIFOs including the clock-domain-crossing version.
  8. 8
    VLG-07 · Verilog by Example: The 140-Example Lab Bank Practise with about 140 short designs, each with a testbench, grouped by topic so you can drill one skill at a time.
  9. 9
    VLG-05 · FPGA Primitives (Xilinx) Instantiate the device's own primitives where the synthesizer's inference is not enough.

Capstone

Self-checking FIFO with a clock-domain crossing (CAP-11)

Take the first course

Every course in the path can be taken on its own, in any order.

VLG-01