VLG-01 · Digital Design with Verilog
Your first hardware, written as code.
Learn to think in parallel. Write the same circuit in three styles and know why each style exists.
You build: combinational and sequential modules that match their truth tables.
Prefer to be taught it live? FPGA Design for Software Engineers (FPG-101, 4 days) is the same material delivered in a scheduled cohort by an instructor, in person or online. See the live course · Live dates
Promise
Write your first modules in three styles, and know why each one exists.
Prerequisites
basic digital logic (gates, truth tables).
Units
1. The design flow Study guide: `hdl_design_ch01`
where HDL fits between specification and silicon; a short history of the standards; why synthesizable style matters.
2. Modules and structure `hdl_design_ch02`
module anatomy, instantiation, port connection by name and by position, gate and switch primitives.
3. Dataflow `hdl_design_ch03`
continuous assignment, the operator table, width rules, reduction and shift operators, carry-lookahead example.
4. Behaviour `hdl_design_ch04`
`always` blocks, sensitivity lists, blocking versus non-blocking, `if` and `case`, loops and their hardware meaning.
Labs
Each lab names its environment and a pass check. Labs are not marked complete on "it ran" — the pass check has to hold.
| Lab | What you do | Environment |
|---|---|---|
| VLG-01ach ch 1–2 | Half adder in three stylesPass check: All three match on all four inputs | sim60 min |
| VLG-01bch ch 3 | 4-bit adder with carry-lookaheadPass check: Matches the behavioural adder | sim60 min |
| VLG-01cch ch 4 | Counter with blocking and non-blocking assignmentsPass check: Waveform explains the difference | sim60 min |
Capstone project · CAP-11
Self-Checking FIFO with Clock-Domain Crossing · 2 weeks
A block must pass data between two clocks at unknown ratios.
Implement the FIFO with Gray-coded pointers. Verify with a self-checking testbench across three clock ratios.
Deliverables: RTL, testbench, coverage report, synthesis report.
Outcomes
- I can write the same half adder in gate, dataflow, and behavioural style and explain the differences.
- I can choose between `=` and `<=` in a clocked block and say why.
- I can read a port list and wire an instance without guessing the order.
Also in
How it runs
Work through the units in order. Each unit groups the chapters of the study guide with its share of the labs. You can start any time; there is no cohort date and nothing expires.
Labs run in a VM, a container, a simulator or on real hardware, and the card above names which. Where a lab needs hardware — an RDMA NIC, a programmable switch model, an FPGA — there is a simulator fallback so you are never blocked by equipment.
Questions
Do I get a certificate?
You get a completion record for the course. Path badges and project credentials are earned by passing the labs and the project review, not by attendance.
Can my team take this together?
Yes — and if you would rather have it delivered live, with the instructor in the room, this course also exists as a scheduled live cohort. See the live dates.
How long does it take?
≈ 12 h of study including the labs. Most engineers take it part-time over a few weeks.