VLG-08 · Digital Design with Verilog
Every controller is a state machine. Build them on purpose.
Draw the state diagram, code it as three blocks, and choose the encoding that fits your target: area, power or speed.
You build: Moore and Mealy detectors, encoded three ways, with a comparison of flip-flops and frequency.
In final review — the chapters for this course are still being finalised.
Promise
Design, code, and verify Moore and Mealy controllers and sequence detectors, and choose a state encoding for area, power, or speed.
Prerequisites
VLG-01 and VLG-02 (testbench basics). VLG-03 recommended.
Units
1. Verilog foundations for FSMs Study guide: `fsm_ch01_verilog_foundations`
combinational and sequential constructs, the latch trap, testbench basics, the three-block FSM structure.
2. Moore machines and a toggle design `fsm_ch02_moore_fsm`
state diagrams, design planning, RTL, simulation, schematic check.
3. Mealy machines `fsm_ch03_mealy_fsm`
the same toggle as a Mealy machine, excitation table, testbench.
4. Overlapping 101 detectors `fsm_ch04_sequence_detectors`
Moore and Mealy state tables, RTL, state-count comparison.
5. State encoding for area, power, and speed `fsm_ch05_state_encoding`
binary, Gray, one-hot; switching power; trade-offs.
6. Controllers and data and control paths `fsm_ch06_controllers_and_practice`
registered-pulse controller, control and data partition, practice set.
Labs
Each lab names its environment and a pass check. Labs are not marked complete on "it ran" — the pass check has to hold.
| Lab | What you do | Environment |
|---|---|---|
| VLG-08ach ch 3–4 | Moore toggle with an enable, state diagram firstPass check: Output changes only on enabled edges | sim90 min |
| VLG-08bch ch 6 | Overlapping 101 detector, MoorePass check: Matches the reference trace on a 20-bit stream | sim90 min |
| VLG-08cch ch 7 | Same detector as Mealy; compare state countsPass check: Both traces equal; state counts stated | sim90 min |
| VLG-08dch ch 8–9 | Binary, Gray and one-hot encodings; flip-flop and frequency tablePass check: Table with all three; recommendation stated | sim120 min |
Capstone project · CAP-21
FSM Controller with a Data Path · 2 weeks
A serial sensor sends 16-bit words. The count of ones must be computed in hardware, and a controller must sequence the count.
Build an FSM controller that drives a 16-bit ones counter. It starts on a request, samples the word, raises a one-cycle done pulse, and ignores new requests while busy. Choose the state encoding for a stated clock target, and justify Moore or Mealy for each output.
Deliverables: RTL, testbench, state diagram, encoding comparison table, one-page design note.
Outcomes
- I can draw Moore and Mealy state diagrams for an overlapping pattern and state the state count of each.
- I can code an FSM as three always blocks and explain each sensitivity list.
- I can say when one-hot encoding is worth its flip-flops, and when Gray is the better choice.
- I can split a controller from its data path and register the handshake between them.
Also in
How it runs
Work through the units in order. Each unit groups the chapters of the study guide with its share of the labs. You can start any time; there is no cohort date and nothing expires.
Labs run in a VM, a container, a simulator or on real hardware, and the card above names which. Where a lab needs hardware — an RDMA NIC, a programmable switch model, an FPGA — there is a simulator fallback so you are never blocked by equipment.
Questions
Do I get a certificate?
You get a completion record for the course. Path badges and project credentials are earned by passing the labs and the project review, not by attendance.
Can my team take this together?
Yes — and if you would rather have it delivered live, with the instructor in the room, this course also exists as a scheduled live cohort. See the live dates.
How long does it take?
≈ 10 h of study including the labs. Most engineers take it part-time over a few weeks.