VLG-06 · Digital Design with Verilog
The blocks every digital team rebuilds.
CRC, PRBS, RAM and FIFO: the applied blocks you will be asked for in your first week, built and checked.
You build: a CRC, a PRBS generator and an asynchronous FIFO, each with a test.
In final review — the chapters for this course are still being finalised.
Promise
Build the blocks that appear in almost every real design: CRC, pseudo-random generators, dual-port RAM, and FIFOs including the clock-domain-crossing version.
Prerequisites
VLG-03.
Units
1. Typical circuits `huawei_typical_circuits`, section 1
adders, data-path blocks, flip-flop family, ALU, FSM encodings.
2. CRC section 5, CRC
the polynomial, serial and parallel generators.
3. Random sequences and RAM models section 5, PRBS and RAM
.
4. FIFOs section 5, synchronous and asynchronous
empty and full logic, Gray-code pointers.
Labs
Each lab names its environment and a pass check. Labs are not marked complete on "it ran" — the pass check has to hold.
| Lab | What you do | Environment |
|---|---|---|
| VLG-06ach cookbook | Serial vs parallel CRC on random dataPass check: Identical on 10,000 frames | sim90 min |
| VLG-06bch cookbook | PRBS periodPass check: Period equals 255 | sim60 min |
| VLG-06cch cookbook | Synchronous FIFOPass check: Full and empty correct | sim90 min |
| VLG-06dch cookbook | Asynchronous FIFO, two clocksPass check: No data lost at two rate ratios | sim120 min |
Capstone project · CAP-11
Self-Checking FIFO with Clock-Domain Crossing · 2 weeks
A block must pass data between two clocks at unknown ratios.
Implement the FIFO with Gray-coded pointers. Verify with a self-checking testbench across three clock ratios.
Deliverables: RTL, testbench, coverage report, synthesis report.
Outcomes
- I can prove a parallel CRC matches the serial one on random data.
- I can explain why a FIFO's pointers are Gray-coded when they cross clocks.
- I can size a FIFO and explain its empty and full timing.
Also in
How it runs
Work through the units in order. Each unit groups the chapters of the study guide with its share of the labs. You can start any time; there is no cohort date and nothing expires.
Labs run in a VM, a container, a simulator or on real hardware, and the card above names which. Where a lab needs hardware — an RDMA NIC, a programmable switch model, an FPGA — there is a simulator fallback so you are never blocked by equipment.
Questions
Do I get a certificate?
You get a completion record for the course. Path badges and project credentials are earned by passing the labs and the project review, not by attendance.
Can my team take this together?
Yes — and if you would rather have it delivered live, with the instructor in the room, this course also exists as a scheduled live cohort. See the live dates.
How long does it take?
≈ 10 h of study including the labs. Most engineers take it part-time over a few weeks.