Hardware Acceleration Engineer

Who it is for

cloud, NFV, and FPGA-minded network engineers.

The sequence

1. 1
   VLG-01 · Verilog Foundations: Modules, Dataflow, Behaviour Write your first modules in three styles, and know why each one exists.
2. 2
   VLG-03 · Combinational, Sequential and Memory Design Design combinational blocks from truth tables, sequential blocks from state diagrams, and memory from IP or a compiler.
3. 3
   VLG-04 · Synthesis-Ready RTL and Hardware Mapping Read your RTL the way a synthesizer does: know which constructs become wires, latches, flip-flops, or priority logic, and fix the ones that surprise you.
4. 4
   OFL-01 · SmartNIC and DPU Acceleration Decide what belongs on the card, program a SmartNIC or DPU, and deploy accelerated workloads on Kubernetes.
5. 5
   OFL-02 · Crypto NIC and TLS Offload Offload TLS to hardware, configure real servers to use it, and prove the throughput and CPU gains.
6. 6
   OFL-03 · PCIe Passthrough and Virtual Network Performance Choose between passthrough, SR-IOV, virtio, and accelerated vSwitches for a workload, and measure the difference.
7. 7
   OFL-04 · SR-IOV: Principles and Practice Build an SR-IOV lab from scratch and run it in a VM, a container, and a cloud platform.
8. 8
   VLG-05 · FPGA Primitives (Xilinx) Instantiate the device's own primitives where the synthesizer's inference is not enough.