FPG-220 · FPGA & Acceleration

FPGA SoC & High-Speed Interfaces

Zynq-class SoCs and the high-speed links around them: PS-PL co-design over AXI, gigabit transceivers, Aurora and 10G Ethernet.

Advanced 4 days in person8 half-days online Max 14 in person

Who this course is for

FPGA engineers moving onto SoC devices and high-speed links, and embedded engineers integrating a Zynq-class platform into a product.

Prerequisites

Working Verilog or VHDL and a completed FPGA design flowFPG-101 or equivalent experienceComfort with a logic analyser and an oscilloscope

The detailed curriculum behind this course. The library holds the lesson-level curriculum for this ground — every lesson named, in order. Take it as the syllabus map, or work through it yourself with the all-access library.

FPGA Stage 2: ZYNQ, High-Speed Interfaces & Algorithms 200 lessons · Advanced
MIPI CSI-2 + DDR3 Video Pipeline on Artix-7 46 lessons · Intermediate

Course outline

Day 1 — SoC architecture and PS-PL integration

Zynq UltraScale+ architecture: processing system, programmable logic, and the interfaces between
AXI4, AXI4-Lite and AXI-Stream: handshakes, bursts and throughput arithmetic
Address maps, memory-mapped IP and interrupt routing
Building a custom AXI peripheral and bringing it up from Linux

Day 2 — Moving data between PS and PL

AXI DMA and XDMA: descriptor chains, scatter-gather and completion handling
Cache coherency, memory barriers, and what the CPU actually observes
Bandwidth budgeting: finding where the data path saturates first
Zero-copy paths and when they are worth the complexity

Day 3 — Gigabit transceivers

SerDes architecture: PMA, PCS, reference clocks and line rates
Equalisation, pre-emphasis and reading an eye diagram
Aurora and 10G Ethernet MACs on a real link
High-speed converter interfaces: LVDS and JESD204 basics

Day 4 — Bring-up and debug

Timing closure with high-speed IO and rate-changing clock domains
ILA, VIO and eye scan for link debug
Link-training failures: clocking, reset sequencing and reference quality
Writing a bring-up log someone else can follow

What you build

Not exercises with a known answer. Each project is built, measured and defended by you, on hardware and a kernel version you actually run — so the result is something you can take back to your team.

The custom AXI peripheral

Design and integrate a memory-mapped AXI4-Lite peripheral with interrupt support, then write the Linux side that drives it and measure the round-trip latency.

You leave withthe RTL, the driver, and a measured latency budget for the register path

DMA bandwidth investigation

Build a PS-PL data path over AXI DMA, then find the bottleneck by measurement — memory, fabric or descriptor handling — and fix the one that actually limits it.

You leave witha bandwidth study with the binding constraint identified and corrected

High-speed link bring-up dossier

Bring up a gigabit transceiver link from cold: reference clock, reset sequencing, equalisation, and an eye measurement, documented so another engineer can repeat it.

You leave witha bring-up dossier with eye diagrams and the failure modes you eliminated

Hands-on labs

Labs follow the academy model — 35% principles, 20% guided investigation, 45% engineering studio. Every claim you make in a lab is backed by a trace, a counter or a measurement you captured yourself. How we teach

Lab: build a custom AXI4-Lite peripheral, map it into the PS address space and drive it from Linux
Lab: move a frame through AXI DMA with a scatter-gather descriptor chain and measure the achieved bandwidth
Lab: bring up a gigabit link and measure the eye opening at the receiver
Lab: close timing on a design with a rate-changing clock domain crossing at the high-speed interface
Lab: debug a deliberately broken link with ILA and eye scan, and identify the cause from evidence

This course uses lab hardware. In-person cohorts get boards on the desk; online cohorts get remote board access over SSH and JTAG.

Capstone project

Bring up a complete SoC data path: a custom AXI peripheral, a DMA stream between PL and PS memory, and a high-speed link carrying real traffic — with a bring-up log recording every failure you hit, the evidence that identified it, and the fix.

What you leave with

PS-PL integration you built rather than copied from a demo
AXI and DMA throughput arithmetic you can defend at design review
Gigabit link bring-up and debug with real measurements
A bring-up log format your team can reuse

How it runs

Every course follows the same model: 35% principles, 20% guided investigation, 45% engineering studio. You leave with working code, raw measurements and an evidence-based report — not a certificate of attendance. Read the methodology or see a full sample lesson.

Material is adapted to your kernel version, hardware and workload before a private delivery. For public cohorts, the environment is provided and configured.

Questions

Who is this course for?

FPGA engineers moving onto SoC devices and high-speed links, and embedded engineers integrating a Zynq-class platform into a product. It sits at advanced level within the FPGA & Acceleration track.

What do I need to know already?

Specific prerequisites for this course: Working Verilog or VHDL and a completed FPGA design flow; FPG-101 or equivalent experience; Comfort with a logic analyser and an oscilloscope. We confirm levels before the cohort starts and adapt if a group is stronger or weaker than expected.

Can this run privately for my team?

Yes. Any course runs on-site at your offices anywhere, or live online for a distributed team, with labs adapted to your hardware and codebase.

What is the difference between in-person and online?

In person is 4 full days with hardware on your desk, capped at 14. Online is 8 half-day sessions across about two weeks so you can keep working, capped at 20, with remote lab access.

Do you invoice companies?

Yes. Purchase orders are accepted and invoicing is available in USD, EUR, GBP, SAR and CAD.

Upcoming dates

Dates	Where	Seats	Early bird	Regular
1 Nov – 10 Nov 20268 half-days	Gulf bandLive online · 14:00–18:00 GST	3 of 20	—	US$2,900
2 Nov – 11 Nov 20268 half-days	Europe bandLive online · 14:00–18:00 CET	8 of 20	—	US$2,900
9 Nov – 18 Nov 20268 half-days	Americas bandLive online · 13:00–17:00 ET	13 of 20	—	US$2,900
18 Oct – 21 Oct 20264 full days	RiyadhIn person · KAFD Conference Centre	7 of 14	—	SAR 15,000
25 Oct – 28 Oct 20264 full days	Kuwait CityIn person · Al Hamra Tower	12 of 14	—	USD 4,000
25 Oct – 28 Oct 20264 full days	MuscatIn person · Knowledge Oasis Muscat	7 of 14	—	USD 4,000
2 Nov – 5 Nov 20264 full days	OttawaIn person · Kanata North Tech Park	12 of 14	—	CAD 5,440
9 Nov – 12 Nov 20264 full days	TorontoIn person · MaRS Discovery District	7 of 14	—	CAD 5,440
9 Nov – 12 Nov 20264 full days	LondonIn person · Shoreditch Works	12 of 14	—	GBP 3,120
16 Nov – 19 Nov 20264 full days	BerlinIn person · Factory Görlitzer Park	7 of 14	EUR 3,310until 17 Oct	~~EUR 3,680~~

Dates shown for the next few months. If nothing fits, tell us where and when — cohorts are added on demand, and private delivery can be scheduled any week.

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