FPG-220 · FPGA & Acceleration · Advanced
FPGA SoC & High-Speed Interfaces — full syllabus
Zynq-class SoCs and the high-speed links around them: PS-PL co-design over AXI, gigabit transceivers, Aurora and 10G Ethernet.
Who this course is for
FPGA engineers moving onto SoC devices and high-speed links, and embedded engineers integrating a Zynq-class platform into a product.
Prerequisites
- Working Verilog or VHDL and a completed FPGA design flow
- FPG-101 or equivalent experience
- Comfort with a logic analyser and an oscilloscope
Course outline
Day 1 — SoC architecture and PS-PL integration
- Zynq UltraScale+ architecture: processing system, programmable logic, and the interfaces between
- AXI4, AXI4-Lite and AXI-Stream: handshakes, bursts and throughput arithmetic
- Address maps, memory-mapped IP and interrupt routing
- Building a custom AXI peripheral and bringing it up from Linux
Day 2 — Moving data between PS and PL
- AXI DMA and XDMA: descriptor chains, scatter-gather and completion handling
- Cache coherency, memory barriers, and what the CPU actually observes
- Bandwidth budgeting: finding where the data path saturates first
- Zero-copy paths and when they are worth the complexity
Day 3 — Gigabit transceivers
- SerDes architecture: PMA, PCS, reference clocks and line rates
- Equalisation, pre-emphasis and reading an eye diagram
- Aurora and 10G Ethernet MACs on a real link
- High-speed converter interfaces: LVDS and JESD204 basics
Day 4 — Bring-up and debug
- Timing closure with high-speed IO and rate-changing clock domains
- ILA, VIO and eye scan for link debug
- Link-training failures: clocking, reset sequencing and reference quality
- Writing a bring-up log someone else can follow
Hands-on labs
- Lab: build a custom AXI4-Lite peripheral, map it into the PS address space and drive it from Linux
- Lab: move a frame through AXI DMA with a scatter-gather descriptor chain and measure the achieved bandwidth
- Lab: bring up a gigabit link and measure the eye opening at the receiver
- Lab: close timing on a design with a rate-changing clock domain crossing at the high-speed interface
- Lab: debug a deliberately broken link with ILA and eye scan, and identify the cause from evidence
Capstone project
Bring up a complete SoC data path: a custom AXI peripheral, a DMA stream between PL and PS memory, and a high-speed link carrying real traffic — with a bring-up log recording every failure you hit, the evidence that identified it, and the fix.
What you leave with
- PS-PL integration you built rather than copied from a demo
- AXI and DMA throughput arithmetic you can defend at design review
- Gigabit link bring-up and debug with real measurements
- A bring-up log format your team can reuse
Upcoming dates
| Dates | Where | Seats | Early bird | Regular | |
|---|---|---|---|---|---|
| 1 Nov – 10 Nov 20268 half-days | Gulf bandLive online · 14:00–18:00 GST | 3 of 20 | — | US$2,900 | |
| 2 Nov – 11 Nov 20268 half-days | Europe bandLive online · 14:00–18:00 CET | 8 of 20 | — | US$2,900 | |
| 9 Nov – 18 Nov 20268 half-days | Americas bandLive online · 13:00–17:00 ET | 13 of 20 | — | US$2,900 | |
| 18 Oct – 21 Oct 20264 full days | RiyadhIn person · KAFD Conference Centre | 7 of 14 | — | SAR 15,000 | |
| 25 Oct – 28 Oct 20264 full days | Kuwait CityIn person · Al Hamra Tower | 12 of 14 | — | USD 4,000 | |
| 25 Oct – 28 Oct 20264 full days | MuscatIn person · Knowledge Oasis Muscat | 7 of 14 | — | USD 4,000 | |
| 2 Nov – 5 Nov 20264 full days | OttawaIn person · Kanata North Tech Park | 12 of 14 | — | CAD 5,440 | |
| 9 Nov – 12 Nov 20264 full days | TorontoIn person · MaRS Discovery District | 7 of 14 | — | CAD 5,440 | |
| 9 Nov – 12 Nov 20264 full days | LondonIn person · Shoreditch Works | 12 of 14 | — | GBP 3,120 | |
| 16 Nov – 19 Nov 20264 full days | BerlinIn person · Factory Görlitzer Park | 7 of 14 | EUR 3,310until 17 Oct |
Book a seat, or bring this course to your team
Seats can be reserved online; private delivery runs on-site or live online, adapted to your stack.
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