FPGA Stage 2: ZYNQ, High-Speed Interfaces & Algorithms
A five-month advanced FPGA programme on the Zynq-7035: SoC design, GT transceivers, PCIe, SATA, LVDS and full projects.
Advanced200 lessons
video
FPGA High-Speed Interfaces & SoC · 200 video lessons
Outcomes
- Design Zynq PS-PL systems with AXI-Lite, AXI-Full, AXI-Stream and AXI-DMA
- Bring up GT transceivers, Aurora, 64B/66B and 10G Ethernet/UDP stacks
- Build a PCIe (XDMA/RIFFA) data-transfer system and a multi-channel terminal project
Where we teach this
- FPG-220 · FPGA SoC & High-Speed Interfaces live cohort
- FPG-101 · FPGA Design for Software Engineers live cohort
The lessons
Every lesson in this curriculum, in the order we teach it.
- 0TCP stack basics: timeout and bandwidth demo
- 1Course introduction
Beginner supplement
- 1Ethernet CRC-32 checker module
Zynq design
- 1Course guide and syllabus overview
- 2FPGA and Zynq: the story behind SoC development
- 3Zynq basics, step 1: the Zynq SoC architecture
- 4Developing FPGA projects on Zynq: a guided tour
- 5Multi-channel DDR3 read/write design using a block design
- 6Block-design approach: two BRAM interconnect modes
- 7AXI-Lite bus explained
- 8AXI-Lite bus code implementation
- 9AXI-Lite master: code simulation and verification
- 10AXI4-Full protocol explained
- 11AXI4-Full master module code
- 11Supplement: AXI4-Full master module simulation and verification
- 12Summary of PL-side logic design
- 13PS development environment: building ARM software on the Xilinx platform
- 14PS basics, step 1: the C development environment and tips
- 15SDK debugging workflow and methods
- 16Three ways to use GPIO on Zynq, part 1
- 17Three ways to use GPIO on Zynq, part 2
- 18Three ways to use GPIO on Zynq, part 2
- 19PS-side UART controller: usage and design
- 20Flash code refinement and on-board debugging
- 20PS-side SPI flash controller: usage and design
- 21PS-side I2C EEPROM controller: usage and design
- 22PS-PL interaction options, part 1: AXI M GP interface
- 23PS-PL interaction over AXI M GP, part 2: PL-side debugging 1
- 24PS-PL interaction over AXI M GP, part 2: PL-side debugging 2
- 25PS-PL interaction over AXI S HP: bulk data transfer
- 26PS-PL interaction with AXI DMA, episode 1
- 27PS-PL interaction with AXI DMA, episode 2
- 28lwIP TCP, episode 1: introducing the lwIP stack
- 29lwIP TCP, episode 1: timers and interrupts, part 1
- 30lwIP TCP, episode 1: timers and interrupts, part 2
- 30lwIP TCP client code walkthrough
- 30TCP server code and on-board testing
- 31High-speed interfaces, step 1: GT transceiver primer
- 31PL-triggered PS interrupts and multi-source interrupt design
Zynq project
- 0Zynq-01: project overview and design approach for a Zynq data-transfer and control board
- 0Zynq-02: WDMA design overview
- 0Zynq-03: WDMA FIFO submodule code and simulation
- 0Zynq-04: WDMA control submodule code and simulation
- 0Zynq-05: WDMA AXI4 submodule code and simulation
- 0Zynq-06: WDMA interrupt submodule code and simulation
- 0Zynq-07: WDMA overall simulation waveforms
- 0Zynq-08: fixing WDMA issues
- 0Zynq-09: building a PL-PS transfer system with WDMA
- 0Zynq-10: integrating and debugging the PL-PS interaction system with our own WDMA design
- 0Zynq-11: adding TCP communication on the PS side and tuning TCP performance
High-speed interfaces
- 32High-speed interfaces, step 1: GT transceiver basics, part 1
- 33High-speed interfaces, step 1: GT transceiver basics, part 2
- 34Xilinx GT transceiver configuration with examples
- 35GT transceiver official example project and first steps with high-speed transceivers
- 36Optical fibre basics
- 37IBERT: GT transceiver eye-diagram testing
- 378B/10B encoding: underlying principles
- 38Custom-protocol PHY layer design on a GT transceiver, part 1
- 39GT transceiver PHY layer design, part 2
- 40GT transceiver PHY transmit module design, part 1
- 41GT PHY layer design complete
- 42GT PHY layer: TX module simulation and debugging
- 43GT PHY layer: RX module simulation and debugging
- 44LFSR pseudo-random generator module design
- 45GT PHY layer: TX module with a PRBS generator and periodic COMMA insertion
- 46GT PHY layer: additions and on-board verification
- 47Aurora 8B/10B lesson 1: fundamentals
- 48Aurora 8B/10B IP configuration, part 1
- 48Aurora 8B/10B IP configuration, part 2
- 49Aurora 8B/10B framework code
- 50Aurora 8B/10B on-board test and results
- 5164B/66B encoding explained
- 52GT 64B/66B IP core configuration
- 53GT 64B/66B official example walkthrough
- 54Slip bits and manual alignment in GT 64B/66B
- 55Custom 64B/66B PHY design, part 1
- 56Custom 64B/66B PHY code, part 2
- 57Custom 64B/66B PHY code, part 3
- 58Custom 64B/66B PHY simulation results and walkthrough
- 59Custom 64B/66B PHY on hardware: results
- 60Aurora 64B/66B project setup
- 61Aurora 64B/66B project verification
- 62SRIO introduction and IP configuration
- 63SRIO: Hello AXI-Stream transfer packet format
- 64SRIO framework code
- 65SRIO packet-transfer module code
- 66SRIO: simulation and on-board debugging
- 67Dynamic MMCM reconfiguration through DRP: principles and approach
- 68Dynamic MMCM frequency change through DRP: code walkthrough
- 69FPGA 10G Ethernet, lesson 1: 10G Ethernet PCS/PMA fundamentals, part 1
- 70FPGA 10G Ethernet, lesson 1: official PCS/PMA simulation example, part 1
- 71Part G: using the PCS/PMA IP module
- 7210G Ethernet PHY layer implementation and on-board verification
- 7310G Ethernet MAC layer, part 1: MAC RX code and simulation
- 7410G Ethernet MAC layer, part 2: CRC32 in MAC RX code and simulation
- 7510G Ethernet MAC layer, part 3: CRC processing module code and simulation
- 7610G Ethernet MAC layer, part 4: MAC TX module code and simulation
- 7710G Ethernet MAC layer, part 5: overall MAC revisions and on-board test
- 7810G Ethernet MAC layer, part 6: transmit debugging and on-board speed test
- 79Ethernet basics
- 8010G Ethernet IP layer, part 1: IP RX module code and simulation
- 8110G Ethernet IP layer, part 2: IP TX module code and simulation
- 8210G Ethernet ARP layer: ARP RX, ARP TX and ARP table code and simulation
- 8310G Ethernet ICMP layer: ICMP TX and RX code and simulation
- 8410G Ethernet arbiter module code and simulation
- 8510G Ethernet UDP layer: UDP RX and TX code and simulation
- 8610G UDP stack design: overall stack composition and simulation
- 87First on-board loopback test of the 10G UDP stack
- 8810G UDP stack complete: on-board debugging and bug fixes
- 8910G UDP stack loopback and full-rate transmit tests
- 89Supplement: 10G UDP stack jumbo-frame fragmentation and reassembly design
- 90PCIe learning roadmap and key concepts
- 91PCIe basics: history and hardware fundamentals
- 92PCIe introduction: topology, configuration space and BARs explained
- 93XDMA IP core configuration in detail
- 94XDMA and DDR data-transfer project design
- 95Preparing for XDMA hardware testing
- 96XDMA hardware test results
- 97XDMA interrupts and host-software testing
- 98High-speed multi-channel terminal, lesson 1: project overview, block diagram and design approach
- 99High-speed multi-channel terminal, lesson 2: design steps and link bandwidth calculation
- 100High-speed multi-channel terminal, lesson 3: application packet design
- 101High-speed multi-channel terminal, lesson 3: project setup
- 102High-speed multi-channel terminal, lesson 3: first on-board test of three high-speed inputs
- 103High-speed multi-channel terminal, lesson 4: width conversion, clock-domain crossing and AXI4
- 104High-speed multi-channel terminal, lesson 4: memory-manager code design and simulation
- 105High-speed multi-channel terminal, lesson 4: BRA and interrupt control module
- 106High-speed multi-channel terminal, lesson 4: code refinement
- 107High-speed multi-channel terminal, lesson 4: bug fixes before on-board testing
- 108High-speed multi-channel terminal, lesson 4: first hardware test results
- 108Supplement: interrupts in the multi-channel high-speed interface, and improving the interrupt mechanism
- 109High-speed multi-channel terminal, lesson 5: project block diagram and code review
- 110Multi-channel high-speed protocol terminal: 2 fibre links, 1 gigabit link and PCIe host demo
- 111Part G: multi-lane communication design and GT channel bonding
- 112PCIe communication with RIFFA: porting the code
- 113RIFFA driver installation and read/write test
Algorithms
- 0LZW-01: LZW algorithm principles and flow chart
- 0LZW-02: compression and decompression code and simulation
- 0SM3-01: SM3 algorithm and how it works
- 0SM3-02: SM3 code walkthrough
- 0SM3-03: SM3 simulation and C debugging
- 0SM3-04: SM3 on-board test results
- 0SM4-01: SM4 algorithm and how it works
- 0SM4-02: SM4 Verilog walkthrough, simulation and comparison with C
- 0SM4-03: SM4 on-board test on the ZYNQ-7035
LVDS
- 0LVDS-01: LVDS fundamentals and course overview
- 0LVDS-02: the basic LVDS electrical standard
- 0LVDS-03: the IODELAY primitive
- 0LVDS-04: XAPP585 clock-pair phase alignment code
- 0LVDS-04: XAPP585 application note walkthrough
- 0LVDS-05: XAPP585 data-line sampling point and skew adjustment
- 0LVDS-06: XAPP585 simulation walkthrough
- 0LVDS-07: Camera Link protocol and industrial camera basics
- 0LVDS-08: Camera Link camera project setup and on-board test
Remote upgrade
- 0MultiBoot 01: FPGA configuration basics
- 0MultiBoot 02: MultiBoot design walkthrough
- 0MultiBoot 03: the STARTUPE2 primitive and flash read/write test
- 0MultiBoot 04: Ethernet and remote-upgrade module
- 0MultiBoot 05: review, state-machine transitions, packets and host-software flow
- 0MultiBoot 06: FPGA code optimisation and first dual-image download
- 0MultiBoot 07: remote upgrade demo with the host software
- 0MultiBoot 08: Qt host-software source walkthrough
SATA
- 5SATA specification: PHY-layer state machine
- 6PHY code, part 1: GT transceiver overview
- 7SATA 3.0 GT transceiver configuration
- 8PHY code, part 2: using the GT transceiver
- 9PHY code, part 3: PHY controller module, part 1
- 10PHY code, part 3: PHY controller module, part 2
- 11PHY layer top-level design: pin assignment and timing constraints
- 12PHY layer on-board debugging and testing
- 13Link-layer fundamentals
- 14Link layer in detail
- 15Writing the link-layer code, part 1
- 16Writing the link-layer code, part 2
- 17Writing the link-layer code, part 3: CRC and LFSR
- 18Writing the link-layer code, part 4: transmit and receive data handling
- 19Writing the link-layer code, part 5: primitives, scrambling and descrambling
- 20Link-layer code simulation, part 1: first simulation
- 21Link-layer code simulation, part 2: deeper simulation
- 22Link-layer code: on-board debugging and project issues
- 23The transport layer: FIS packet structure
- 24The transport layer: ATA-8 command set
- 25DMA module code walkthrough
- 26Code walkthrough: data read/write self-test module
- 27On-board read/write data testing
- 28SATA 3.0 protocol stack: drive test with Samsung and Colorful SSDs
- 28SATA 3.0 protocol stack: drive test with Samsung and Colorful SSDs (part 41)
- 0FPGA SATA protocol course 1: introduction
- 0FPGA SATA protocol course 2: navigating the SATA specification
- 0FPGA SATA protocol course 3: SATA specification basics
- 0FPGA SATA protocol course 4: the SATA PHY layer and OOB protocol
USB 3.0
- 1USB 3.0 chip overview and reading the datasheet
- 2USB 3.0 chip CYUSB3014: schematic and PCB design
- 3PCB outline definition and component placement
- 4PCB rules, layer stack-up and impedance-controlled trace widths
- 5Type-C differential-pair routing
- 6CYUSB3014 development environment
- 7CYUSB3014 firmware development
- 8CYUSB3014 and FPGA code walkthrough
- 9CYUSB3014 read/write test on hardware
All-access library
Every curriculum on this page, with the labs and lab sequences, for a year.