Train your team

FPGA & Digital Design Engineer

From a blank file to a synthesizable design that meets timing on real silicon.

5 courses 70 hours of instructionBadge: FPGA Engineer

Who it is for

Digital designers and software engineers moving into FPGA work.

The sequence

  1. 1
    VLG-101 · Verilog Foundations, Logic and Structure Design ≈ 12 h guided
  2. 2
    VLG-201 · RTL Design & Synthesis-Ready Verilog ≈ 12 h guided
  3. 3
    FPG-101 · FPGA Design for Software Engineers 4 days
  4. 4
    FPG-110 · Vivado Timing Closure & STA 3 days
  5. 5
    FPG-201 · Linux Drivers for FPGA Accelerators 3 days

Bridges both delivery formats: VLG-101 and VLG-201 are guided self-paced, FPG-101/110/201 are live cohorts.

Capstone

Design, verify and close timing on a working block, then move it onto real hardware with an ILA capture that agrees with simulation.

Start with the first course

Every course in the path can be taken on its own. Dates are on the course page.

VLG-101