MIPI CSI-2 + DDR3 Video Pipeline on Artix-7

FPGA High-Speed Interfaces & SoC · 46 video lessons

Outcomes

• Receive MIPI CSI-2 data: PHY, byte/lane alignment and packet parsing
• Buffer frames in DDR3 through an AXI4 interface and drive HDMI output
• Debug real image-corruption problems with simulation and on-board tools

Where we teach this

• FPG-220 · FPGA SoC & High-Speed Interfaces live cohort
• VIS-101 · MIPI CSI-2, GMSL2 & Multi-Camera Synchronization live cohort

The lessons

Every lesson in this curriculum, in the order we teach it.

• 2Tool installation
• 3Solution overview
• 4Part A: UART receiver timing design
• 4Part B: UART receiver module code
• 4Part C: UART receiver simulation and on-board verification
• 5DDR3 operating principles
• 6DDR3 IP configuration and example project walkthrough
• 7Part A: DDR3 IP ports
• 7Part B: DDR3 IP AXI4 interface timing
• 8Part A: exercise: writing to DDR3 over AXI4
• 8Part B: exercise: writing to DDR3 over AXI4
• 9Supplement: using the FIFO IP
• 10Part A: writing UART data to DDR3
• 10Part B: writing UART data to DDR3
• 10Part C: writing UART data to DDR3
• 11Supplement: VGA display driver principles
• 12Driving HDMI colour bars from an FPGA
• 13Part A: reading DDR3 over AXI for HDMI display
• 13Part B: reading DDR3 over AXI for HDMI display
• 13Part C: reading DDR3 over AXI for HDMI display
• 14Introduction to the MIPI CSI-2 protocol
• 15MIPI receiver architecture overview
• 16Part A: I2C read/write timing
• 16Part B: I2C read/write timing
• 17OV5640 configuration module walkthrough
• 18MIPI serial-to-parallel conversion
• 19MIPI byte-alignment module design
• 20Part A: MIPI lane data-channel alignment module
• 20Part B: MIPI lane-alignment module code
• 21Part A: MIPI packet parser design approach
• 21Part B: MIPI packet parser timing and code
• 22Part A: MIPI module simulation and verification
• 22Part B: MIPI module on-board verification
• 23Converting MIPI byte data to pixel format
• 24Writing MIPI RAW data to DDR3 and displaying it
• 24Debug A: image error analysis
• 24Debug B: image error analysis
• 24Debug C: image error analysis
• 24Debug D: image error analysis
• 24Debug E: image error analysis
• 25Part A: MIPI RAW-to-RGB module (Bayer to RGB)
• 25Part B: MIPI RAW-to-RGB module design
• 26Gamma correction implementation
• 27Part A: project summary
• 27Part B: project summary
• 27Part C: project summary