Labs
Labs are the unit of progress, not videos. Every lab names its chapters, its environment, its time budget, what you submit and a pass check that either holds or does not. Nothing is marked complete on "it ran".
Environments
vm— a Linux virtual machine, no special hardware.container— Docker or kind.sim— a simulator or emulator: SoftRoCE, veth and network namespaces, DPDK tap PMDs, bmv2 for P4, Verilator or Icarus for Verilog.hardware— a real NIC, switch, DPU, GPU or FPGA board. Every hardware lab has a simulator fallback where one exists.
Lab sequences
The sequences are the main lab unit for experienced engineers. Each starts from a situation rather than a command: a ticket, an outage, a design request. Faults are injected and you have to find them. Stages build on each other, every stage has acceptance tests and evidence to hand in, and each sequence ends with a timed graded practical.
Sequence 1 · Packet Path Forensics ≈ 12 h · 4 stages · graded practical 90 min
A payments service reports intermittent 40 ms stalls on a Linux host. No errors are logged. Your lead wants the stall located to a layer, with evidence, before anyone touches the application.
Stage 1 — Reproduce and measure
Build a two-namespace topology with an injected delay on one hop. Reproduce the stall with a request loop.
Acceptance: stall reproduced in at least 9 of 10 runs; the injected delay is visible in the measurements.
Evidence: latency histogram, command log.
Stage 2 — Trace the path
Instrument the receive and transmit paths with eBPF tracing (PDP-02 tools). Attribute each millisecond of the request to a stage.
Acceptance: the tracer's total matches the client measurement within 10%.
Evidence: per-stage table.
Stage 3 — Find the cause
A second fault is injected: a conntrack table near its limit. Find it using counters, not logs.
Acceptance: the fault is named with the counter that proves it, and the learner's fix removes the stall.
Evidence:
Stage 4 — Write the record
A 1-page incident note: timeline, layer, evidence, fix, and what would have caught this earlier.
Acceptance: a reviewer who did not run the lab can state the root cause from the note alone.
Evidence:
Sequence 2 · Userspace Dataplane Builder ≈ 40 h · 4 stages · graded practical 3 h
A startup needs a software gateway that forwards 10 Gb/s of small packets on two cores. You own the data-plane component. Requirements are in the brief.
Stage 1 — Bring up the dataplane
EAL, ports, and a poll-mode receive loop on `net_tap` or a virtual NIC. Run `testpmd` to baseline.
Acceptance: no mbuf leaks after 10 million packets (checked with mempool statistics); forwarding rate recorded.
Evidence:
Stage 2 — Protocol layers
Add ARP, IPv4, ICMP, and UDP handling to your stack. Interoperate with the kernel.
Acceptance: `ping` and a UDP echo pass against a Linux peer, with 0 checksum errors on 1,000 packets.
Evidence:
Stage 3 — Stateful path
Add a flow table, an ACL, and NAT. Inject a fault: flows collide in the hash table under load.
Acceptance: under 1 million flows, no flow is misrouted; collision count is reported and bounded.
Evidence:
Stage 4 — Performance under constraint
Pin cores, size pools for the burst size, and remove any allocation from the fast path.
Acceptance: the fast path makes zero heap allocations (verified with a counter), and the rate meets the brief on the target machine. The brief's rate is set by the lab lead.
Evidence:
Sequence 3 · RDMA Fabric Operations ≈ 45 h · 5 stages · graded practical 3 h
An AI training cluster on RoCEv2 is losing 25% of its all-reduce throughput since a switch change. The lab is a four-host fabric with a broken configuration. (Hardware-required. The recorded-counter variant is in Stage 2.)
Stage 1 — Verbs and measurement
Write a two-sided and a one-sided RDMA test with completion handling that never leaks work requests. Build a repeatable benchmark.
Acceptance: 1,000,000 operations with no leaked work requests; latency and throughput reported with repeat-run variance.
Evidence:
Stage 2 — Find the lossless fault
Reproduce the slowdown across all host pairs. Read pause and drop counters on each port. Identify the port and priority responsible.
Acceptance: the faulty port and priority named from counters. The recorded-counter variant requires the same answer from a captured dataset.
Evidence:
Stage 3 — Fix and prove
Correct the configuration on a branch, then run at 80% load for 10 minutes.
Acceptance: zero RDMA drops; pause frames on the lossless class under the stated limit; p99 latency under the stated bound.
Evidence:
Stage 4 — MPI on the fabric
Run an OSU latency and bandwidth test under OpenMPI with UCX. Change one transport parameter and measure its effect.
Acceptance: before-and-after table with a statistically stated difference.
Evidence:
Stage 5 — Change record
Root cause, blast radius, rollback, verification evidence. **Graded practical.** A second fault, with a different symptom, on a fresh fabric, in 3 hours. Senior variant: the fault is an ECN threshold that reacts too late. ---
Acceptance:
Evidence:
Sequence 4 · Cluster Network Engineering ≈ 40 h · 4 stages · graded practical 3 h
Two Kubernetes clusters must share services across a region. A security review requires that only named services cross, encrypted, and that every crossing is observable.
Stage 1 — Build the network
Create a CNI plugin with the correct ADD and DEL behaviour. Verify pod-to-pod and cross-node paths.
Acceptance: pods reach each other across nodes; DEL releases the address and the interface, verified after 100 create-delete cycles.
Evidence:
Stage 2 — Policy
Apply default-deny. Add the allowed flows only.
Acceptance: every allowed flow works; every denied flow times out; the test suite covers each rule.
Evidence:
Stage 3 — Cross-cluster
Connect the clusters. Enable mutual TLS between services.
Acceptance: the named service is reachable; a non-named service is not; captured traffic is encrypted.
Evidence:
Stage 4 — Observe and fail
Inject a fault into the mesh's routing. Find it from the SLA dashboard, not from logs.
Acceptance: alert fires within the defined window; the root cause is named with its metric.
Evidence:
Sequence 5 · Zero-Trust Gateway Engineering ≈ 50 h · 5 stages · graded practical 3 h
A regulated customer needs a gateway that enforces identity-based access to internal APIs at a line rate, with TLS terminated in hardware where available, and with compliance evidence.
Stage 1 — Policy engine
Write a default-deny policy with identity, device posture, and resource attributes. Test it with a decision table.
Acceptance: every row in the decision table produces the expected decision; a changed attribute flips the decision.
Evidence:
Stage 2 — Enforcement path
Put enforcement on the data path. Add an eBPF or DPDK filter that enforces the decisions.
Acceptance: decisions match enforcement on 100,000 flows with no mismatch.
Evidence:
Stage 3 — TLS and cost
Offload or accelerate TLS where available; measure CPU per connection with and without.
Acceptance: CPU per connection reduced by the stated amount, with the measurement method documented.
Evidence:
Stage 4 — Fault
A certificate rotation causes intermittent failures. Diagnose it with telemetry.
Acceptance: root cause named, fix proven, and an alert added that would have fired first.
Evidence:
Stage 5 — Evidence
Map the controls to two regulatory clauses and name the evidence for each. **Graded practical.** Given a policy change request, assess its risk, implement it on a branch, test it, and produce the evidence. ---
Acceptance:
Evidence:
Sequence 6 · Programmable Network Operations ≈ 40 h · 3 stages · graded practical 3 h
A team wants to change forwarding behaviour safely: a P4 pipeline for a new service, tested automatically before any change reaches the staging network.
Stage 1 — P4 pipeline
Implement a parser and match-action stages for a new header. Control the tables from a P4Runtime client.
Acceptance: the pipeline forwards the test vectors correctly; a table update takes effect within the stated time.
Evidence:
Stage 2 — Automated test
Build a regression suite with traffic generation (TRex or Scapy) and counter checks.
Acceptance: the suite fails on a seeded bug and passes on the fix; each run produces a machine-readable report.
Evidence:
Stage 3 — Telemetry gate
Add a telemetry check that blocks promotion when loss or latency regresses beyond the threshold.
Acceptance: a seeded regression blocks promotion; a clean run promotes.
Evidence:
Sequence 7 · Offload Decision and Deployment ≈ 60 h · 4 stages · graded practical 4 h
A cloud team wants to move a virtual switch's work to a SmartNIC or DPU. Management asks for a yes or no, with numbers, and a plan if the answer is yes.
Stage 1 — Baseline
Measure the virtual switch on the host: throughput, CPU per gigabit, and p99 latency for three packet sizes.
Acceptance: baseline table with repeat runs and variance.
Evidence:
Stage 2 — Offload
Enable offload on the card or the DPU. Confirm which flows are offloaded and which fall back.
Acceptance: offloaded-flow count is stated and reconciled with the traffic mix.
Evidence:
Stage 3 — Hardware detail (Verilog)
Write a small RTL block for one fast-path function (for example a header-field match), with a self-checking testbench and a synthesis check that reports no unintended latches.
Acceptance: testbench passes on 10,000 random vectors; synthesis report clean.
Evidence:
Stage 4 — Decide
Compare host and offload results on the same workload. Write the decision with the numbers and the failure cases.
Acceptance: decision record names the workload where offload loses, and why.
Evidence:
Sequence 8 · 5G User-Plane Engineering ≈ 50 h · 4 stages · graded practical 3 h
A mobile operator needs a user-plane function for a private 5G network. Your scope is forwarding, charging records, and one network slice.
Stage 1 — Tunnel path
Parse GTP-U, look up the tunnel endpoint, forward and decapsulate.
Acceptance: 100% of test traffic forwarded with correct TEID handling; malformed packets counted, not forwarded.
Evidence:
Stage 2 — Charging
Produce usage records from forwarded bytes, with the reporting interval set by the brief.
Acceptance: records reconcile with forwarded byte counts to within the stated tolerance.
Evidence:
Stage 3 — Slice and latency
Give one slice a separate queue and priority. Measure the latency budget under load.
Acceptance: slice latency stays under the bound at the stated load; the other slice is unaffected.
Evidence:
Stage 4 — Failure
Kill one forwarding instance during a session. Recover with state.
Acceptance: session survives or is re-established within the stated time; lost-packet count reported.
Evidence:
Sequence 9 · Network Performance Investigation ≈ 36 h · 4 stages · graded practical 3 h
A video service reports stalls on mobile networks, but the same encoder runs well on wired links. Your task is to find out whether the transport is the cause and to propose a change that is measured, not guessed.
Stage 1 — Reproduce on a profile
Build a network emulator profile for the mobile case: bandwidth variation, loss, and jitter. Reproduce the stall.
Acceptance: stall reproduced at the stated rate across repeat runs.
Evidence:
Stage 2 — Measure the transport
Capture the sender's congestion state and retransmissions.
Acceptance: a time series showing the cause, not just the effect.
Evidence:
Stage 3 — Experiment
Compare the current algorithm with a variant on the same profile, with confidence intervals.
Acceptance: the comparison states whether the difference is real, using a stated test.
Evidence:
Stage 4 — Recommend
Write the change proposal with risk, rollback, and the monitoring that would show regression. **Graded practical.** Given a new profile, decide whether the transport is the cause, in 3 hours. ---
Acceptance:
Evidence:
Sequence 10 · Verilog to Silicon-Ready RTL ≈ 40 h · 4 stages · graded practical 3 h
A junior engineer's module has been rejected at review for synthesis issues and simulation mismatches. Your job is to fix it, prove the fix, and document the rules that were broken.
Stage 1 — Find the defects
Run the lint and synthesis reports. Classify each warning as real or noise.
Acceptance: each real defect listed with its rule and line.
Evidence:
Stage 2 — Self-checking testbench
Write a testbench with a reference model and randomized stimulus.
Acceptance: 100,000 random vectors pass; the testbench fails on a seeded bug.
Evidence:
Stage 3 — Fix
Correct latches, sensitivity lists, and blocking assignments in clocked logic. Keep the function.
Acceptance: same testbench passes; synthesis report has no unintended latches.
Evidence:
Stage 4 — Pipeline and sharing
Add a pipeline stage to meet a clock target; share an arithmetic unit where the area budget requires.
Acceptance: target met in the timing report; latency stated.
Evidence:
Sequence 11 · Verilog into Packet Hardware ≈ 45 h · 4 stages · graded practical 3 h
A NIC team needs an ingress block that checks frame CRC at line rate and drops bad frames, with statistics.
Stage 1 — CRC
Implement serial and parallel CRC. Prove they are equivalent on random frames.
Acceptance: identical results on 10,000 frames, including runt and oversize frames.
Evidence:
Stage 2 — Ingress with backpressure
Add a FIFO between the clock domains and handle backpressure.
Acceptance: no frame lost or duplicated under the stated rate ratio; the testbench checks this.
Evidence:
Stage 3 — Statistics
Count good, bad, and dropped frames; expose them through a register interface.
Acceptance: counters match the testbench's own count.
Evidence:
Stage 4 — Integrate
Run the block in a software packet path (DPDK or a simulator) against captured traffic.
Acceptance: the same frames are accepted and rejected as in RTL.
Evidence:
Sequence 12 · FSM Controller Engineering ≈ 20 h · 4 stages · graded practical 2 h
A serial receiver feeds a pattern detector. The detector was rejected at review: it misses matches that overlap, and its synthesis report shows an unintended latch.
Stage 1 — Diagram
Draw the Moore and the Mealy state diagrams for an overlapping 1-0-1 detector. State the number of states for each.
Acceptance: both machines reproduce the reference output on the given 20-bit stream; the state counts are stated.
Evidence: both diagrams, the state table, the output trace.
Stage 2 — RTL in three blocks
Code the state register, the next-state logic, and the output logic as separate blocks. Give every case a default.
Acceptance: no latch warnings in the elaboration log; the output sensitivity list matches the machine type.
Evidence:
Stage 3 — Verify and find the bug
Write a testbench with a reference model. A missing default is seeded into one copy; the testbench must catch it.
Acceptance: the testbench fails on the seeded bug, passes after the fix, and passes 10,000 random input bits.
Evidence:
Stage 4 — Encoding trade
Implement binary, Gray, and one-hot versions of one machine. Record the flip-flop count, the logic depth, and the maximum frequency for each.
Acceptance: a table with all three; the learner recommends one and states what it costs.
Evidence:
Sequence 13 · RTL Timing and Area Closure ≈ 25 h · 4 stages · graded practical 3 h
An eight-bit ALU misses its target clock in review, and its area is over budget. Fix both without changing what it computes.
Stage 1 — Datapath
Build the eleven-operation ALU with one shared adder and a multiplexer tree. Carry and borrow come from the adder path only.
Acceptance: all eleven operations pass the vector set, including carry-in and borrow cases.
Evidence:
Stage 2 — Budget
Write the register-to-register budget (clock-to-Q plus logic plus setup) for the critical path, and predict the maximum frequency.
Acceptance: the prediction is within 10% of the timing report.
Evidence:
Stage 3 — Reset and crossings
Choose synchronous or asynchronous reset and state why. Add a two-flop synchronizer to a single-bit level signal that enters the ALU from a second clock domain.
Acceptance: a testbench shows the level arrives within two destination-clock cycles and does not glitch the output.
Evidence:
Stage 4 — Close the target
Reduce logic depth by grouping terms and, if needed, add one pipeline stage. Measure each change on its own.
Acceptance: the target is met in the timing report; area and latency before and after are recorded; each change is tied to a measured effect.
Evidence:
Lab bank
Programmable Data Planes
| Lab | Chapter | Env | Min | What you do |
|---|---|---|---|---|
| PDP-01a | ch 05–09 | vm | 60 | Trace one ICMP echo through the stack with a kernel tracerYou name at least 6 hooks in order, with timestamps |
| PDP-01b | ch 23–24 | sim | 60 | Build a netns topology and add a netfilter drop rulePing fails on the rule, passes after removal |
| PDP-01c | ch 27 | vm | 45 | Attach a minimal XDP program and count packetsCounter equals packets sent |
| PDP-02a | ch 05 | vm | 45 | Load a "hello" eBPF program and read its trace outputOutput shows your message |
| PDP-02b | ch 11 | vm | 60 | XDP program that drops ICMPPing fails, TCP still works |
| PDP-02c | ch 16 | sim | 90 | L4 load balancer with a backend mapRequests split across backends |
| PDP-02d | ch 22 | vm | 60 | libbpf user-space loader for lab 02b with a stats printStats match tcpdump counts |
| PDP-03a | ch 05 | vm | 90 | Hand-build a veth CNI pluginTwo pods ping each other |
| PDP-03b | ch 12–13 | container | 90 | Install Cilium and apply a deny policyDenied flow times out, allowed flow works |
| PDP-03c | ch 14 | container | 90 | Connect two kind clustersService reachable from the other cluster |
| PDP-03d | ch 24 | container | 60 | Enable WireGuard encryptionCaptured traffic is encrypted |
| PDP-04a | ch 13 | sim | 90 | First P4 program on bmv2: forward by destinationPackets exit the expected port |
| PDP-04b | ch 21 | sim | 90 | Control a table from a P4Runtime clientTable entries appear and take effect |
| PDP-04c | ch 23 | sim | 90 | Stateless firewall rules in P4Blocked rule drops, others pass |
| PDP-04d | ch 25 | sim | 90 | Simple load balancer in P4Flows split across two ports |
Packet Processing with DPDK
| Lab | Chapter | Env | Min | What you do |
|---|---|---|---|---|
| DPK-01a | ch 02 | vm | 60 | Set up DPDK, bind a NIC or use `net_tap``dpdk-testpmd` starts and reports ports |
| DPK-01b | ch 08–09 | sim | 90 | Ring and mempool receive loopNo mbuf leaks after 10 million packets |
| DPK-01c | ch 12 | sim | 90 | ACL on the fast pathMatching flows dropped, counts correct |
| DPK-01d | ch 21 | sim | 90 | Simple L3 forwarderThroughput measured and recorded |
| DPK-02a | ch 09 | sim | 60 | ICMP echo reply from your stack`ping` gets replies |
| DPK-02b | ch 10 | sim | 60 | UDP echo serviceEcho matches on 1,000 messages |
| DPK-02c | ch 12 | sim | 120 | TCP three-way handshake`tcpdump` shows SYN, SYN-ACK, ACK |
| DPK-02d | ch 21 | sim | 120 | NAT for outbound flowsReplies return to the right client |
| DPK-03a | ch 04–05 | vm | 60 | EAL options and PMD selectionPorts and cores match the flags |
| DPK-03b | ch 20 | vm | 120 | Virtual switch between two VMsVM-to-VM ping works through the switch |
| DPK-03c | ch 23 | vm | 120 | Virtual firewall in a service chainBlocked traffic stops at the firewall |
| DPK-03d | ch 27 | vm | 90 | Chain two network functions and measure latencyAdded latency reported per hop |
RDMA and HPC Interconnect
| Lab | Chapter | Env | Min | What you do |
|---|---|---|---|---|
| RDM-01a | ch 11 | sim | 60 | Hello-world RDMA on SoftRoCESend completes and the message arrives |
| RDM-01b | ch 12 | sim | 60 | RDMA write with a remote keyRemote buffer holds the written data |
| RDM-01c | ch 15 | sim | 60 | Atomic fetch-and-add on a shared counterFinal value equals the number of clients |
| RDM-01d | ch 29 | hardware | 90 | Latency and bandwidth testResults table with two runs |
| RDM-02a | ch 08–09 | hardware | 90 | Configure PFC and ECN on a switch or a simulatorLossless class shows no drops under load |
| RDM-02b | ch 14 | hardware | 60 | Connectivity test across the fabricAll pairs reachable |
| RDM-02c | ch 15 | hardware | 90 | Benchmark with standard toolsReport with throughput and latency |
| RDM-02d | ch 24 | sim | 60 | Find a link fault from countersFault named with the counter that shows it |
| RDM-03a | ch 28 | container | 90 | OSU latency and bandwidth with OpenMPI and UCXBoth results recorded |
| RDM-03b | ch 11 | sim | 60 | Use OFI to list providers and run a testChosen provider reported |
| RDM-03c | ch 16 | sim | 90 | MPI_Put example on two ranksData arrives after fence |
| RDM-03d | ch 22 | sim | 60 | Change one MCA parameter and measureBefore and after compared |
| RDM-04a | ch 13 | sim | 180 | Build Ceph with RDMA`ceph` shows the RDMA messenger |
| RDM-04b | ch 15 | sim | 120 | Deploy a three-node test clusterHealth OK |
| RDM-04c | ch 18 | sim | 90 | Small-block latency: RDMA vs TCPBoth curves in one chart |
| RDM-04d | ch 20 | sim | 60 | CPU use during the same testPer-core usage table |
| RDM-05a | ch 13 | hardware | 60 | NCCL all-reduce testBus bandwidth recorded |
| RDM-05b | ch 17 | hardware | 90 | Micro-benchmark for GPU and NIC pathsTable of message sizes |
| RDM-05c | ch 27 | hardware | 60 | Create and assign SR-IOV virtual functions`lspci` shows the VFs |
| RDM-05d | ch 14 | hardware | 90 | CUDA-aware MPI send and receiveDevice buffers pass correctly |
Hardware Offload and Virtualization
| Lab | Chapter | Env | Min | What you do |
|---|---|---|---|---|
| OFL-01a | ch 14 | hardware | 60 | Check whether OVS offload is activeOffloaded flow count above zero |
| OFL-01b | ch 10 | hardware | 120 | DPDK application on a SmartNICPackets counted at the NIC |
| OFL-01c | ch 19 | hardware | 180 | Custom packet processing on an FPGA SmartNICOutput matches the reference model |
| OFL-01d | ch 21 | hardware | 120 | Run an application on a DPUApplication runs with traffic offloaded |
| OFL-02a | ch 11 | sim | 60 | Enable kTLS and send data`ss` shows the TLS ULP |
| OFL-02b | ch 12 | vm | 90 | nginx with TLS and a session checkHandshake succeeds and cipher is recorded |
| OFL-02c | ch 16 | hardware | 90 | Throughput and CPU with and without offloadTable with both runs |
| OFL-02d | ch 29 | vm | 180 | TLS-offload web clusterLoad test passes |
| OFL-03a | ch 05 | hardware | 60 | Verify the IOMMU and assign a deviceDevice appears in the guest |
| OFL-03b | ch 08 | hardware | 90 | virtio versus VF throughputBoth numbers and the gap explained |
| OFL-03c | ch 10 | hardware | 120 | VPP forwarding in a VMForwarding counters match |
| OFL-03d | ch 17 | hardware | 90 | Tune a VM for low latencyp99 before and after |
| OFL-04a | ch 04 | vm | 60 | Create SR-IOV virtual functionsVFs listed |
| OFL-04b | ch 07 | vm | 60 | Attach a VF to a VMVM sees the NIC |
| OFL-04c | ch 18 | vm | 90 | DPDK on a virtual functionPackets flow |
| OFL-04d | ch 25 | vm | 90 | Performance test on the VFReport produced |
Cloud-Native and Telco Infrastructure
| Lab | Chapter | Env | Min | What you do |
|---|---|---|---|---|
| CNT-01a | ch 07–08 | container | 90 | Istio install and a 90/10 traffic splitSplit measured |
| CNT-01b | ch 09 | container | 60 | mTLS and an authorization policyDenied request shown |
| CNT-01c | ch 19 | container | 120 | Cross-cluster service discoveryRemote service reached |
| CNT-01d | ch 24 | container | 60 | Find a broken route in the meshRoot cause written up |
| CNT-02a | ch 04 | vm | 45 | Size a leaf–spine fabricCalculation sheet |
| CNT-02b | ch 08 | sim | 90 | SDN lab on a simulatorPolicy applied |
| CNT-02c | ch 10 | sim | 60 | NVMe-oF testLatency recorded |
| CNT-02d | ch 30 | vm | 90 | Design review of your own HCI networkReviewed against the checklist |
| CNT-03a | ch 22 | sim | 60 | Parse GTP-U headers from a captureTEID extracted |
| CNT-03b | ch 07 | sim | 90 | Forwarding rules and countersMatched packets equal expected |
| CNT-03c | ch 20 | sim | 120 | DPDK user planeForwarding runs |
| CNT-03d | ch 26 | sim | 60 | Slice a user plane by QoSSlices separated |
Security and Zero Trust
| Lab | Chapter | Env | Min | What you do |
|---|---|---|---|---|
| SEC-01a | ch 05 | vm | 90 | Microsegmentation between three workloadsOnly allowed pairs connect |
| SEC-01b | ch 09 | sim | 90 | Policy evaluation with a default-deny engineDecisions logged |
| SEC-01c | ch 17 | sim | 90 | WAF rule chainAttack blocked, normal request passes |
| SEC-01d | ch 18 | container | 120 | ZTNA access with mTLSAccess granted only with a valid identity |
| SEC-02a | ch 11 | sim | 60 | ACL first-match and countersCounters match |
| SEC-02b | ch 13 | sim | 90 | Stateful session tableSession created, expired |
| SEC-02c | ch 15 | sim | 90 | NAT translationsReplies return correctly |
| SEC-02d | ch 19 | sim | 120 | Tune the firewall data pathThroughput before and after |
Observability, Testing and Automation
| Lab | Chapter | Env | Min | What you do |
|---|---|---|---|---|
| OBS-01a | ch 29 | vm | 120 | Build a telemetry collector in PythonCounters stored as time series |
| OBS-01b | ch 08 | vm | 90 | Anomaly detection on the collected seriesInjected anomaly flagged |
| OBS-01c | ch 09 | vm | 90 | Traffic forecastError reported on a holdout set |
| OBS-01d | ch 10 | vm | 90 | Root-cause analysis on an incidentCorrect cause ranked first |
| OBS-02a | ch 08 | container | 60 | Pod-to-pod latency measurementLatency table |
| OBS-02b | ch 14 | container | 90 | eBPF-based network monitoringMetric visible |
| OBS-02c | ch 16 | container | 90 | Root-cause exercise on an injected faultFault found |
| OBS-02d | ch 28 | container | 60 | Write an SLA and a baselineSLA with its measurement |
| OBS-03a | ch 05–06 | sim | 90 | TRex install and first traffic runCounters read |
| OBS-03b | ch 13 | sim | 90 | Kitune test caseCase runs and reports |
| OBS-03c | ch 18 | sim | 90 | Layer 3 routing testRoutes verified |
| OBS-03d | ch 25 | sim | 60 | Generate a benchmark reportReport reproduced by a second run |
Transport and Edge
| Lab | Chapter | Env | Min | What you do |
|---|---|---|---|---|
| TRN-01a | ch 06 | vm | 90 | Read the BBR code path for one sendPath written with function names |
| TRN-01b | ch 12 | vm | 120 | Load a custom congestion-control moduleSelected per socket |
| TRN-01c | ch 18 | sim | 90 | Compare two algorithms on the same profileChart and conclusion |
| TRN-01d | ch 24 | sim | 90 | Satellite-profile evaluationResult reported |
| TRN-02a | ch 06 | sim | 90 | TSN configuration in a simulatorGate schedule verified |
| TRN-02b | ch 09 | sim | 60 | QoS class for latency trafficLatency for the class lower under load |
| TRN-02c | ch 21 | sim | 90 | Edge simulationLatency budget filled |
| TRN-02d | ch 22 | container | 120 | Open-source edge platformWorkload deployed |
Digital Design with Verilog
| Lab | Chapter | Env | Min | What you do |
|---|---|---|---|---|
| VLG-01a | ch ch 1–2 | sim | 60 | Half adder in three stylesAll three match on all four inputs |
| VLG-01b | ch ch 3 | sim | 60 | 4-bit adder with carry-lookaheadMatches the behavioural adder |
| VLG-01c | ch ch 4 | sim | 60 | Counter with blocking and non-blocking assignmentsWaveform explains the difference |
| VLG-02a | ch ch 5 | sim | 60 | Counter testbench with automatic checksPass and fail both reported |
| VLG-02b | ch ch 5 | sim | 45 | Clock with duty cycle and phase shiftMeasured duty cycle correct |
| VLG-02c | ch ch 5 | sim | 45 | `$monitor` and `$strobe` comparisonExplained in your notes |
| VLG-02d | ch ch 5 | sim | 60 | Timing check on a flip-flopViolation reported |
| VLG-03a | ch ch 6 | sim | 90 | Voting circuit from truth tableMatches the specification table |
| VLG-03b | ch ch 7 | sim | 90 | Modulo-N counter with self-startRecovers from an illegal state |
| VLG-03c | ch ch 7 | sim | 90 | Sequence detector as Mealy and as MooreBoth detect the same sequence |
| VLG-03d | ch ch 8 | sim | 90 | RAM write and read-back testAll addresses match |
| VLG-04a | ch ch 9 | sim | 60 | Find unintended latches in a given moduleAll latches named with their cause |
| VLG-04b | ch ch 9 | sim | 90 | Pipeline a multiply-addLatency and throughput stated |
| VLG-04c | ch ch 9 | sim | 90 | Share one adder across two operationsArea and delay reported |
| VLG-04d | ch ch 9 | sim | 60 | Priority versus parallel caseStructure explained |
| VLG-05a | ch primitives | hardware | 60 | Clock buffer instantiationClock reaches the target |
| VLG-05b | ch primitives | hardware | 90 | Block RAM with initial contentsRead-back correct |
| VLG-05c | ch primitives | hardware | 90 | DSP48 multiply-accumulateOutput matches the model |
| VLG-06a | ch cookbook | sim | 90 | Serial vs parallel CRC on random dataIdentical on 10,000 frames |
| VLG-06b | ch cookbook | sim | 60 | PRBS periodPeriod equals 255 |
| VLG-06c | ch cookbook | sim | 90 | Synchronous FIFOFull and empty correct |
| VLG-06d | ch cookbook | sim | 120 | Asynchronous FIFO, two clocksNo data lost at two rate ratios |
| VLG-07a | ch examples, group 2 | sim | 180 | Procedural examples with testbenchesAll pass |
| VLG-07b | ch examples, group 5 | sim | 180 | Primitive and timing examplesAll pass |
| VLG-07c | ch examples, group 8 | sim | 240 | Application projectsProject runs |
| VLG-07d | ch examples, group 9 | sim | 180 | Memory and arithmetic examplesAll pass |
| VLG-08a | ch ch 3–4 | sim | 90 | Moore toggle with an enable, state diagram firstOutput changes only on enabled edges |
| VLG-08b | ch ch 6 | sim | 90 | Overlapping 101 detector, MooreMatches the reference trace on a 20-bit stream |
| VLG-08c | ch ch 7 | sim | 90 | Same detector as Mealy; compare state countsBoth traces equal; state counts stated |
| VLG-08d | ch ch 8–9 | sim | 120 | Binary, Gray and one-hot encodings; flip-flop and frequency tableTable with all three; recommendation stated |
| VLG-09a | ch ch 3–4 | sim | 60 | Fix an incomplete sensitivity list and an unintended latchSimulation and synthesis agree; no latch warning |
| VLG-09b | ch ch 5–6 | sim | 90 | Shift register with blocking and then non-blocking assignments; predict the register countPredicted count equals the synthesis report |
| VLG-09c | ch ch 7–8 | sim | 90 | Priority encoder with `casez` and a default; reorder assignments and verifySame function after every reordering |
| VLG-09d | ch ch 10 | sim | 90 | Compute fmax from clock-to-Q, logic and setup; check against the timing reportWithin 10% of the report |