VLG-09 · Digital Design with Verilog
From code to a clock speed you can defend.
Write RTL that simulates and synthesizes as intended, then measure its critical path and close the timing target with evidence.
You build: an 8-bit ALU with a timing budget, an area report and a closure log.
In final review — the chapters for this course are still being finalised.
Promise
Write RTL that simulates and synthesizes as intended, then measure its timing and area.
Prerequisites
VLG-01 (Verilog syntax).
Units
1. Design flow and why HDL Study guide: `rtl_ch01_design_flow_and_hdl`
specification to bitstream, architecture versus micro-architecture, why not C.
2. Concurrency, instantiation, and a Vivado project `rtl_ch02_concurrency_and_tools`
.
3. The always block and sensitivity lists `rtl_ch03_always_blocks`
`reg` outputs, incomplete lists, `@(*)`.
4. Bitwise operators, if-else, nested if-else, case `rtl_ch04_conditionals_and_latches`
priority versus parallel logic, unintended latches.
5. Intentional latches, testbenches, and the event queue `rtl_ch05_latches_testbenches_and_scheduling`
.
6. Counters and blocking versus non-blocking `rtl_ch06_counters_assignments_and_latches`
2-bit counter from a state table, shift-register failure and fix.
7. casez, casex, functions, tasks, fork-join, delays `rtl_ch07_case_variants_functions_and_delays`
.
8. Grouping logic and assignment order `rtl_ch08_grouping_and_assignment_order`
parentheses and balanced trees.
9. FSM basics and RTL strategy `rtl_ch09_fsm_rtl_strategy`
three always blocks, Moore and Mealy RTL.
10. Register-to-register timing and fmax; complex designs `rtl_ch10_timing_and_complex_design`
.
11. Practice set `rtl_ch11_practice_and_exercises`
reset styles, synchronizers, display tasks, ALU area optimization, exercise map.
Labs
Each lab names its environment and a pass check. Labs are not marked complete on "it ran" — the pass check has to hold.
| Lab | What you do | Environment |
|---|---|---|
| VLG-09ach ch 3–4 | Fix an incomplete sensitivity list and an unintended latchPass check: Simulation and synthesis agree; no latch warning | sim60 min |
| VLG-09bch ch 5–6 | Shift register with blocking and then non-blocking assignments; predict the register countPass check: Predicted count equals the synthesis report | sim90 min |
| VLG-09cch ch 7–8 | Priority encoder with `casez` and a default; reorder assignments and verifyPass check: Same function after every reordering | sim90 min |
| VLG-09dch ch 10 | Compute fmax from clock-to-Q, logic and setup; check against the timing reportPass check: Within 10% of the report | sim90 min |
Capstone project · CAP-22
Timing and Area Closure for an 8-bit ALU · 2 weeks
An eight-bit ALU with eleven operations misses its clock target in review, and its area budget is tight.
Implement the ALU with one shared adder and a multiplexer tree, with registered inputs and outputs. Compute the register-to-register budget, find the critical path in the timing report, and close the target by reducing logic depth or adding one pipeline stage. Report the area before and after.
Deliverables: RTL, testbench with vectors, timing table, area table, change list with the rule behind each change.
Outcomes
- I can find an unintended latch from its warning and fix it by covering every path.
- I can reorder assignments in a clocked block and predict the register count before synthesis.
- I can compute fmax from clock-to-Q, logic, and setup for the critical register path.
- I can place a two-flop synchronizer on a single-bit crossing and say why it does not fix a multi-bit bus.
Also in
How it runs
Work through the units in order. Each unit groups the chapters of the study guide with its share of the labs. You can start any time; there is no cohort date and nothing expires.
Labs run in a VM, a container, a simulator or on real hardware, and the card above names which. Where a lab needs hardware — an RDMA NIC, a programmable switch model, an FPGA — there is a simulator fallback so you are never blocked by equipment.
Questions
Do I get a certificate?
You get a completion record for the course. Path badges and project credentials are earned by passing the labs and the project review, not by attendance.
Can my team take this together?
Yes — and if you would rather have it delivered live, with the instructor in the room, this course also exists as a scheduled live cohort. See the live dates.
How long does it take?
≈ 16 h of study including the labs. Most engineers take it part-time over a few weeks.