ICD-101 · Digital Design & Silicon
IC Design & Silicon Foundations
How a design becomes silicon: the digital implementation flow, physical design, timing sign-off, test and tape-out.
Who this course is for
Digital designers moving from FPGA to ASIC, and hardware engineers who need to understand what happens between RTL and a working chip.
Prerequisites
The detailed curriculum behind this course. The library holds the lesson-level curriculum for this ground — every lesson named, in order. Take it as the syllabus map, or work through it yourself with the all-access library.
- IC Design from Beginner to Master 40 lessons · Intermediate
Course outline
Day 1 — From RTL to gates
- Logic synthesis: what the tool actually does to your RTL
- Technology libraries: standard cells, drive strengths, PVT corners
- Design constraints (SDC): clocks, input and output delays, exceptions
- Reading synthesis reports: area, timing, and what to fix first
- Why 'it synthesises' is not the same as 'it will work'
Day 2 — Physical design
- Floorplanning: die size, aspect ratio, macro placement, power planning
- Placement: congestion, timing-driven placement and legalisation
- Clock tree synthesis: skew, insertion delay and useful skew
- Routing: global vs detailed, crosstalk and antenna rules
Day 3 — Timing, power and sign-off
- Static timing analysis: setup, hold, recovery/removal, multi-corner sign-off
- Fixing violations: useful skew, upsizing, restructuring, pipelining
- Power: dynamic vs leakage, clock gating, multi-Vt, power gating, UPF basics
- Signal integrity: crosstalk delay, IR drop and electromigration
Day 4 — Test, tape-out and the analog boundary
- Design for test: scan insertion, ATPG, compression and coverage closure
- Analog and mixed-signal interfaces a digital block must survive
- Pad rings, ESD, IO standards and packaging
- Tape-out: DRC/LVS, GDSII, mask making and the foundry handoff
What you build
Not exercises with a known answer. Each project is built, measured and defended by you, on hardware and a kernel version you actually run — so the result is something you can take back to your team.
The constraint set that tells the truth
Write an SDC set from a timing diagram alone, then deliberately over-constrain the design and show exactly what breaks and why — the failure mode that hides real problems.
You leave withan audited SDC file and a written account of what over-constraining masked
Pre- versus post-layout timing
Synthesise, place and route one block, then quantify the timing delta between the two views and explain each cause: clock tree, parasitics, crosstalk.
You leave witha before/after timing comparison with a cause attributed to every changed path
Coverage closure on real logic
Insert scan, run ATPG, find the logic that is untestable, and either fix it or document why it cannot be tested.
You leave withan ATPG coverage report and a justified list of remaining untestable logic
Hands-on labs
Labs follow the academy model — 35% principles, 20% guided investigation, 45% engineering studio. Every claim you make in a lab is backed by a trace, a counter or a measurement you captured yourself. How we teach
- Lab: synthesise a small RTL block against a real standard-cell library and read the area, timing and power reports
- Lab: write an SDC constraint set from a timing diagram, then audit it for over-constraining
- Lab: floorplan and place a block, then compare pre- and post-layout timing on the same path
- Lab: insert scan chains, run ATPG, and analyse the coverage and pattern-count report
- Lab: run DRC and LVS on a finished block and triage each class of violation
Capstone project
Take a block from RTL to signed-off GDSII: synthesise, constrain, place and route it, close timing at the target frequency, insert test logic, and pass DRC and LVS — with a sign-off report that explains every violation you waived and why.
What you leave with
- The digital implementation flow end to end, with the trade-offs named
- SDC constraints you wrote and defended rather than inherited
- Timing and power sign-off reports you can read and act on
- A tape-out checklist covering test, DRC/LVS and the foundry handoff
How it runs
Every course follows the same model: 35% principles, 20% guided investigation, 45% engineering studio. You leave with working code, raw measurements and an evidence-based report — not a certificate of attendance. Read the methodology or see a full sample lesson.
Material is adapted to your kernel version, hardware and workload before a private delivery. For public cohorts, the environment is provided and configured.
Questions
Who is this course for?
Digital designers moving from FPGA to ASIC, and hardware engineers who need to understand what happens between RTL and a working chip. It sits at advanced level within the Digital Design & Silicon track.
What do I need to know already?
Specific prerequisites for this course: Solid Verilog or VHDL; Basic digital logic and timing concepts; No ASIC implementation experience required. We confirm levels before the cohort starts and adapt if a group is stronger or weaker than expected.
Can this run privately for my team?
Yes. Any course runs on-site at your offices anywhere, or live online for a distributed team, with labs adapted to your hardware and codebase.
What is the difference between in-person and online?
In person is 4 full days with hardware on your desk, capped at 14. Online is 8 half-day sessions across about two weeks so you can keep working, capped at 20, with remote lab access.
Do you invoice companies?
Yes. Purchase orders are accepted and invoicing is available in USD, EUR, GBP, SAR and CAD.
Upcoming dates
| Dates | Where | Seats | Early bird | Regular | |
|---|---|---|---|---|---|
| 25 Oct – 3 Nov 20268 half-days | Gulf bandLive online · 14:00–18:00 GST | 18 of 20 | — | US$2,900 | |
| 2 Nov – 11 Nov 20268 half-days | Europe bandLive online · 14:00–18:00 CET | 7 of 20 | — | US$2,900 | |
| 2 Nov – 11 Nov 20268 half-days | Americas bandLive online · 13:00–17:00 ET | 12 of 20 | — | US$2,900 | |
| 11 Oct – 14 Oct 20264 full days | RiyadhIn person · KAFD Conference Centre | 12 of 14 | — | SAR 15,000 | |
| 18 Oct – 21 Oct 20264 full days | Kuwait CityIn person · Al Hamra Tower | 7 of 14 | — | USD 4,000 | |
| 25 Oct – 28 Oct 20264 full days | MuscatIn person · Knowledge Oasis Muscat | 12 of 14 | — | USD 4,000 | |
| 26 Oct – 29 Oct 20264 full days | OttawaIn person · Kanata North Tech Park | 7 of 14 | — | CAD 5,440 | |
| 2 Nov – 5 Nov 20264 full days | TorontoIn person · MaRS Discovery District | 12 of 14 | — | CAD 5,440 | |
| 9 Nov – 12 Nov 20264 full days | LondonIn person · Shoreditch Works | 7 of 14 | — | GBP 3,120 | |
| 9 Nov – 12 Nov 20264 full days | BerlinIn person · Factory Görlitzer Park | 12 of 14 | — | EUR 3,680 |
Dates shown for the next few months. If nothing fits, tell us where and when — cohorts are added on demand, and private delivery can be scheduled any week.
