ARC-300 · Processor Architecture
Systems Programming Across x86-64, Arm64 & RISC-V
The privilege models, paging architectures, exception handling and memory models of the big three architectures — compared in source code and tested under QEMU and real silicon.
Who this course is for
Kernel developers, compiler engineers, hypervisor authors, and firmware engineers who need deep, comparative mastery of privileged execution across the three dominant processor architectures.
Prerequisites
Course outline
Day 1 — x86-64 privileged architecture
- Privilege rings 0–3, descriptor tables, task state segments (TSS), and the flat model
- x86-64 4-level and 5-level paging, page table entries, CR3, and TLB invalidation (INVLPG)
- Interrupt and exception handling: IDT, interrupt gates, and local/I/O APIC programming
- Model-Specific Registers (MSRs), CPUID discovery, and syscall/sysret transitions
Day 2 — Arm64 (AArch64) privileged architecture
- Exception levels: EL0 (user), EL1 (OS kernel), EL2 (hypervisor), EL3 (secure monitor)
- Translation regimes, VMSA page tables, TTBR0_EL1/TTBR1_EL1, and ASIDs
- Generic Interrupt Controller (GICv3/v4): distributor, redistributors, and ITS
- System registers (SCTLR_EL1, ESR_EL1, FAR_EL1) and exception vectors
Day 3 — RISC-V privileged architecture
- Privilege modes: Machine (M), Supervisor (S), and User (U) mode
- Control and Status Registers (CSRs): sstatus, scause, sepc, and satp
- Sv39 and Sv48 virtual memory schemes, page table layout, and SFENCE.VMA
- PLIC and Core Local Interruptor (CLINT), and the Supervisor Binary Interface (SBI)
Day 4 — Memory models & concurrency across architectures
- Total Store Order (x86 TSO) vs weak memory models (Arm64, RISC-V)
- Store buffers, invalidation queues, and hardware memory reordering in action
- Instruction barriers, data memory barriers, and acquire-release semantics
- Atomic instructions: LOCK prefix (x86) vs Load-Linked/Store-Conditional vs atomics (LSE/A-extension)
Day 5 — ABIs, payloads & cross-architecture development
- System V x86-64 ABI vs ARM AAPCS64 vs RISC-V Calling Conventions
- Writing portable inline assembly and compiler barriers
- Building minimal bare-metal supervisor payloads across all three architectures in QEMU
- Remote debugging bare-metal targets with GDB and hardware JTAG probes
What you build
Not exercises with a known answer. Each project is built, measured and defended by you, on hardware and a kernel version you actually run — so the result is something you can take back to your team.
The multi-arch boot payload
Write a clean, minimal supervisor-mode payload that configures page tables, sets up exception vectors, and boots to a hello-world banner under QEMU on x86-64, Arm64, and RISC-V.
You leave witha single buildable repository supporting all three target architectures
The memory consistency litmus test
Implement multi-threaded litmus tests in assembly demonstrating Message Passing and Store Buffer reordering differences between x86 TSO and Arm64/RISC-V weak memory models.
You leave withempirical test runs showing reordering frequencies across architectures
The cross-architecture ABI validator
Construct a test suite validating register preservation, argument passing, stack alignments, and system call conventions across x86-64, Arm64, and RISC-V compilers.
You leave withan ABI conformance testing tool with detailed validation logs
Hands-on labs
Labs follow the academy model — 35% principles, 20% guided investigation, 45% engineering studio. Every claim you make in a lab is backed by a trace, a counter or a measurement you captured yourself. How we teach
- Lab: step through system call entry and stack switching on x86-64, Arm64, and RISC-V in QEMU
- Lab: construct an architectural page table hierarchy manually for all three ISAs and inspect translations
- Lab: configure and handle an interrupt dispatch cycle on x86 APIC, Arm GICv3, and RISC-V PLIC
- Lab: demonstrate hardware store reordering on Arm64/RISC-V that never occurs on x86-64
- Lab: compile and boot a minimal multi-architecture supervisor payload that prints to UART across all three targets
Capstone project
Author a cross-architecture privileged bootstrap payload in C and assembly that initializes virtual memory page tables, installs an exception vector table, handles a timer interrupt, and enters user mode across x86-64, Arm64, and RISC-V.
What you leave with
- Fluency moving between x86-64, Arm64, and RISC-V privileged systems code
- Deep intuitive understanding of hardware memory consistency models
- Ability to build, run, and debug bare-metal payloads in QEMU across multiple targets
- Confidence reading CPU architectural manuals and writing porting layers
How it runs
Every course follows the same model: 35% principles, 20% guided investigation, 45% engineering studio. You leave with working code, raw measurements and an evidence-based report — not a certificate of attendance. Read the methodology or see a full sample lesson.
Material is adapted to your kernel version, hardware and workload before a private delivery. For public cohorts, the environment is provided and configured.
Questions
Who is this course for?
Kernel developers, compiler engineers, hypervisor authors, and firmware engineers who need deep, comparative mastery of privileged execution across the three dominant processor architectures. It sits at advanced level within the Processor Architecture track.
What do I need to know already?
Specific prerequisites for this course: Strong C and assembly reading fluency; Solid operating systems knowledge (virtual memory, interrupts); Familiarity with QEMU or hardware boards. We confirm levels before the cohort starts and adapt if a group is stronger or weaker than expected.
Can this run privately for my team?
Yes. Any course runs on-site at your offices anywhere, or live online for a distributed team, with labs adapted to your hardware and codebase.
What is the difference between in-person and online?
In person is 5 full days with hardware on your desk, capped at 14. Online is 10 half-day sessions across about two weeks so you can keep working, capped at 20, with remote lab access.
Do you invoice companies?
Yes. Purchase orders are accepted and invoicing is available in USD, EUR, GBP, SAR and CAD.
Upcoming dates
| Dates | Where | Seats | Early bird | Regular | |
|---|---|---|---|---|---|
| 11 Oct – 15 Oct 20265 full days | RiyadhIn person · KAFD Conference Centre | 11 of 14 | — | SAR 18,750 | |
| 18 Oct – 22 Oct 20265 full days | Kuwait CityIn person · Al Hamra Tower | 6 of 14 | — | USD 5,000 | |
| 25 Oct – 29 Oct 20265 full days | MuscatIn person · Knowledge Oasis Muscat | 11 of 14 | — | USD 5,000 | |
| 25 Oct – 5 Nov 202610 half-days | Gulf bandLive online · 09:00–13:00 GMT+3 | 11 of 20 | — | US$3,600 | |
| 26 Oct – 30 Oct 20265 full days | OttawaIn person · Kanata North Tech Park | 6 of 14 | — | CAD 6,800 | |
| 2 Nov – 6 Nov 20265 full days | TorontoIn person · MaRS Discovery District | 11 of 14 | — | CAD 6,800 | |
| 2 Nov – 13 Nov 202610 half-days | Europe bandLive online · 09:00–13:00 CET | 16 of 20 | — | US$3,600 | |
| 9 Nov – 13 Nov 20265 full days | LondonIn person · Shoreditch Works | 6 of 14 | — | GBP 3,900 | |
| 9 Nov – 13 Nov 20265 full days | BerlinIn person · Factory Görlitzer Park | 11 of 14 | — | EUR 4,600 | |
| 9 Nov – 20 Nov 202610 half-days | Americas bandLive online · 13:00–17:00 ET | 5 of 20 | — | US$3,600 |
Dates shown for the next few months. If nothing fits, tell us where and when — cohorts are added on demand, and private delivery can be scheduled any week.
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