ARC-300 · Processor Architecture · Advanced
Systems Programming Across x86-64, Arm64 & RISC-V — full syllabus
The privilege models, paging architectures, exception handling and memory models of the big three architectures — compared in source code and tested under QEMU and real silicon.
Duration5 full days in person · 10 half-days online
Cohortmax 14 in person · 20 online
Pricefrom SAR 18,750 in person · local pricing per city
Delivery35% principles · 20% guided investigation · 45% engineering studio
Who this course is for
Kernel developers, compiler engineers, hypervisor authors, and firmware engineers who need deep, comparative mastery of privileged execution across the three dominant processor architectures.
Prerequisites
- Strong C and assembly reading fluency
- Solid operating systems knowledge (virtual memory, interrupts)
- Familiarity with QEMU or hardware boards
Course outline
Day 1 — x86-64 privileged architecture
- Privilege rings 0–3, descriptor tables, task state segments (TSS), and the flat model
- x86-64 4-level and 5-level paging, page table entries, CR3, and TLB invalidation (INVLPG)
- Interrupt and exception handling: IDT, interrupt gates, and local/I/O APIC programming
- Model-Specific Registers (MSRs), CPUID discovery, and syscall/sysret transitions
Day 2 — Arm64 (AArch64) privileged architecture
- Exception levels: EL0 (user), EL1 (OS kernel), EL2 (hypervisor), EL3 (secure monitor)
- Translation regimes, VMSA page tables, TTBR0_EL1/TTBR1_EL1, and ASIDs
- Generic Interrupt Controller (GICv3/v4): distributor, redistributors, and ITS
- System registers (SCTLR_EL1, ESR_EL1, FAR_EL1) and exception vectors
Day 3 — RISC-V privileged architecture
- Privilege modes: Machine (M), Supervisor (S), and User (U) mode
- Control and Status Registers (CSRs): sstatus, scause, sepc, and satp
- Sv39 and Sv48 virtual memory schemes, page table layout, and SFENCE.VMA
- PLIC and Core Local Interruptor (CLINT), and the Supervisor Binary Interface (SBI)
Day 4 — Memory models & concurrency across architectures
- Total Store Order (x86 TSO) vs weak memory models (Arm64, RISC-V)
- Store buffers, invalidation queues, and hardware memory reordering in action
- Instruction barriers, data memory barriers, and acquire-release semantics
- Atomic instructions: LOCK prefix (x86) vs Load-Linked/Store-Conditional vs atomics (LSE/A-extension)
Day 5 — ABIs, payloads & cross-architecture development
- System V x86-64 ABI vs ARM AAPCS64 vs RISC-V Calling Conventions
- Writing portable inline assembly and compiler barriers
- Building minimal bare-metal supervisor payloads across all three architectures in QEMU
- Remote debugging bare-metal targets with GDB and hardware JTAG probes
Hands-on labs
- Lab: step through system call entry and stack switching on x86-64, Arm64, and RISC-V in QEMU
- Lab: construct an architectural page table hierarchy manually for all three ISAs and inspect translations
- Lab: configure and handle an interrupt dispatch cycle on x86 APIC, Arm GICv3, and RISC-V PLIC
- Lab: demonstrate hardware store reordering on Arm64/RISC-V that never occurs on x86-64
- Lab: compile and boot a minimal multi-architecture supervisor payload that prints to UART across all three targets
Capstone project
Author a cross-architecture privileged bootstrap payload in C and assembly that initializes virtual memory page tables, installs an exception vector table, handles a timer interrupt, and enters user mode across x86-64, Arm64, and RISC-V.
What you leave with
- Fluency moving between x86-64, Arm64, and RISC-V privileged systems code
- Deep intuitive understanding of hardware memory consistency models
- Ability to build, run, and debug bare-metal payloads in QEMU across multiple targets
- Confidence reading CPU architectural manuals and writing porting layers
Upcoming dates
| Dates | Where | Seats | Early bird | Regular | |
|---|---|---|---|---|---|
| 11 Oct – 15 Oct 20265 full days | RiyadhIn person · KAFD Conference Centre | 11 of 14 | — | SAR 18,750 | |
| 18 Oct – 22 Oct 20265 full days | Kuwait CityIn person · Al Hamra Tower | 6 of 14 | — | USD 5,000 | |
| 25 Oct – 29 Oct 20265 full days | MuscatIn person · Knowledge Oasis Muscat | 11 of 14 | — | USD 5,000 | |
| 25 Oct – 5 Nov 202610 half-days | Gulf bandLive online · 09:00–13:00 GMT+3 | 11 of 20 | — | US$3,600 | |
| 26 Oct – 30 Oct 20265 full days | OttawaIn person · Kanata North Tech Park | 6 of 14 | — | CAD 6,800 | |
| 2 Nov – 6 Nov 20265 full days | TorontoIn person · MaRS Discovery District | 11 of 14 | — | CAD 6,800 | |
| 2 Nov – 13 Nov 202610 half-days | Europe bandLive online · 09:00–13:00 CET | 16 of 20 | — | US$3,600 | |
| 9 Nov – 13 Nov 20265 full days | LondonIn person · Shoreditch Works | 6 of 14 | — | GBP 3,900 | |
| 9 Nov – 13 Nov 20265 full days | BerlinIn person · Factory Görlitzer Park | 11 of 14 | — | EUR 4,600 | |
| 9 Nov – 20 Nov 202610 half-days | Americas bandLive online · 13:00–17:00 ET | 5 of 20 | — | US$3,600 |
Book a seat, or bring this course to your team
Seats can be reserved online; private delivery runs on-site or live online, adapted to your stack.
Questions about fit or prerequisites? Email [email protected]. To save this syllabus, print this page to PDF from your browser.