Timing & Net-Delay Case Studies
Six board-level timing case studies: PCB net delay, IO resources, LVDS, high-speed converters and clock networks.
Advanced12 lessons
video
FPGA High-Speed Interfaces & SoC · 12 video lessons
Outcomes
- Diagnose and fix timing violations on real boards with Vivado
- Choose IO standards and IDELAY settings for source-synchronous links
- Plan clock networks (MMCM/BUFG) for high-speed converter designs
Where we teach this
- FPG-110 · Vivado Timing Closure & STA live cohort
The lessons
Every lesson in this curriculum, in the order we teach it.
- 1chip PCB net delay
- 2FX3 timing optimisation
- 3IOB resource timing
- 4AD9361 LVDS net delay, part 2
- 5AD9361 LVDS net delay, part 1
- 6AFE5832 on ZU15EG, part 1
- 7AFE5832 on ZU15EG, part 2
- 8AFE5832 on ZU15EG, part 3
- 9AFE5832 on ZU15EG, part 4
- 10clock network
- 11clock network, part 2
- 12clock network, part 3
All-access library
Every curriculum on this page, with the labs and lab sequences, for a year.