ICD-101 · Digital Design & Silicon · Advanced
IC Design & Silicon Foundations — full syllabus
How a design becomes silicon: the digital implementation flow, physical design, timing sign-off, test and tape-out.
Who this course is for
Digital designers moving from FPGA to ASIC, and hardware engineers who need to understand what happens between RTL and a working chip.
Prerequisites
- Solid Verilog or VHDL
- Basic digital logic and timing concepts
- No ASIC implementation experience required
Course outline
Day 1 — From RTL to gates
- Logic synthesis: what the tool actually does to your RTL
- Technology libraries: standard cells, drive strengths, PVT corners
- Design constraints (SDC): clocks, input and output delays, exceptions
- Reading synthesis reports: area, timing, and what to fix first
- Why 'it synthesises' is not the same as 'it will work'
Day 2 — Physical design
- Floorplanning: die size, aspect ratio, macro placement, power planning
- Placement: congestion, timing-driven placement and legalisation
- Clock tree synthesis: skew, insertion delay and useful skew
- Routing: global vs detailed, crosstalk and antenna rules
Day 3 — Timing, power and sign-off
- Static timing analysis: setup, hold, recovery/removal, multi-corner sign-off
- Fixing violations: useful skew, upsizing, restructuring, pipelining
- Power: dynamic vs leakage, clock gating, multi-Vt, power gating, UPF basics
- Signal integrity: crosstalk delay, IR drop and electromigration
Day 4 — Test, tape-out and the analog boundary
- Design for test: scan insertion, ATPG, compression and coverage closure
- Analog and mixed-signal interfaces a digital block must survive
- Pad rings, ESD, IO standards and packaging
- Tape-out: DRC/LVS, GDSII, mask making and the foundry handoff
Hands-on labs
- Lab: synthesise a small RTL block against a real standard-cell library and read the area, timing and power reports
- Lab: write an SDC constraint set from a timing diagram, then audit it for over-constraining
- Lab: floorplan and place a block, then compare pre- and post-layout timing on the same path
- Lab: insert scan chains, run ATPG, and analyse the coverage and pattern-count report
- Lab: run DRC and LVS on a finished block and triage each class of violation
Capstone project
Take a block from RTL to signed-off GDSII: synthesise, constrain, place and route it, close timing at the target frequency, insert test logic, and pass DRC and LVS — with a sign-off report that explains every violation you waived and why.
What you leave with
- The digital implementation flow end to end, with the trade-offs named
- SDC constraints you wrote and defended rather than inherited
- Timing and power sign-off reports you can read and act on
- A tape-out checklist covering test, DRC/LVS and the foundry handoff
Upcoming dates
| Dates | Where | Seats | Early bird | Regular | |
|---|---|---|---|---|---|
| 25 Oct – 3 Nov 20268 half-days | Gulf bandLive online · 14:00–18:00 GST | 18 of 20 | — | US$2,900 | |
| 2 Nov – 11 Nov 20268 half-days | Europe bandLive online · 14:00–18:00 CET | 7 of 20 | — | US$2,900 | |
| 2 Nov – 11 Nov 20268 half-days | Americas bandLive online · 13:00–17:00 ET | 12 of 20 | — | US$2,900 | |
| 11 Oct – 14 Oct 20264 full days | RiyadhIn person · KAFD Conference Centre | 12 of 14 | — | SAR 15,000 | |
| 18 Oct – 21 Oct 20264 full days | Kuwait CityIn person · Al Hamra Tower | 7 of 14 | — | USD 4,000 | |
| 25 Oct – 28 Oct 20264 full days | MuscatIn person · Knowledge Oasis Muscat | 12 of 14 | — | USD 4,000 | |
| 26 Oct – 29 Oct 20264 full days | OttawaIn person · Kanata North Tech Park | 7 of 14 | — | CAD 5,440 | |
| 2 Nov – 5 Nov 20264 full days | TorontoIn person · MaRS Discovery District | 12 of 14 | — | CAD 5,440 | |
| 9 Nov – 12 Nov 20264 full days | LondonIn person · Shoreditch Works | 7 of 14 | — | GBP 3,120 | |
| 9 Nov – 12 Nov 20264 full days | BerlinIn person · Factory Görlitzer Park | 12 of 14 | — | EUR 3,680 |
Book a seat, or bring this course to your team
Seats can be reserved online; private delivery runs on-site or live online, adapted to your stack.
Questions about fit or prerequisites? Email [email protected]. To save this syllabus, print this page to PDF from your browser.